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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com features l integrated high-performance headphone amplifier l on-chip pll for use with external clock sources l sample rate converters l s/pdif digital audio output l ac 97 2.1 compliant l 20-bit stereo digital-to-analog converters l 18-bit stereo analog-to-digital converters l four analog line-level stereo inputs for line in, cd, video, and aux l two analog line-level mono inputs for modem and internal pc beep l dual microphone inputs l high quality pseudo-differential cd input l integrated high-performance microphone pre-amplifier l separate stereo line-level output l extensive power management support l meets or exceeds the microsoft pc 99 audio performance requirements l crystalclear 3d stereo enhancement l i 2 s serial digital outputs enable cost effective 6-channel audio applications description t he cs4201 is an ac 97 2.1 compatible stereo audio codec designed for pc multimedia systems. using the industry leading crystalclear delta-sigma and mixed signal technology, the cs4201 enables the design of pc 99-compliant desktop, portable, and entertainment pcs, where high-quality audio is required. the cs4201, when coupled with a pci audio accelera- tor or core logic supporting the ac 97 interface, implements a cost effective, superior quality, audio so- lution. the cs4201 surpasses pc 99 and ac 97 2.1 audio quality standards. ordering info cs4201 -kq 48-pin tqfp 9x9x1.4 mm cs4201 -jq 48-pin tqfp 9x9x1.4 mm sep 00 ds483pp2 ac'97 registers line cd aux video mic1 mic2 phone pc_beep line_out hp_out mono_out analog input mux and output mixer ac-link and ac '97 registers pcm_data gain / mute controls input mux s output mixer mixer / mux selects ac- link pwr mgt test sync bit_clk sdata_out sdata_in reset# pcm_data src src id0# id1# gpio, s/pdif serial data port gpio0/lrclk gpio1/sdout eapd/sclk spdo/sdo2 18 bit adc 20 bit dac 3d stereo enhancement s input mixer crystalclear audio codec 97 with headphone amplifier cs4201
cs4201 2 ds483pp2 table of contents 1. characteristics and specifications ........................................................ 5 analog characteristics ................................................................................................. 5 mixer characteristics ................................................................................................... 6 absolute maximum ratings ......................................................................................... 6 recommended operating conditions.......................................................................... 6 digital characteristics .................................................................................................. 7 ac 97 serial port timing............................................................................................. 8 2. general description ....................................................................................... 11 2.1 ac-link ............................................................................................................ 11 2.2 control registers ................................................................................................. 12 2.3 sample rate converters .................................................................................... 12 2.4 output mixers ..................................................................................................... 12 2.5 input mux ............................................................................................................ 12 2.6 volume control ................................................................................................... 12 3. ac-link frame definition ................................................................................ 14 3.1 ac-link serial data output frame ..................................................................... 15 3.2 serial data output slot tags (slot 0) .................................................................. 15 3.3 command address port (slot 1) ......................................................................... 15 3.4 command data port (slot 2) ............................................................................... 16 3.5 pcm playback data (slots 3-11) ........................................................................ 16 3.6 gpio data (slot12) ............................................................................................. 16 3.7 ac-link serial data input frame ....................................................................... 17 3.8 serial data input slot tag bits (slot 0) .............................................................. 17 3.9 status address port (slot 1) ............................................................................... 17 3.10 status data port (slot 2) ................................................................................... 18 3.11 pcm capture data (slot 3-8) ............................................................................ 18 3.12 gpio pin status (slot 12) ................................................................................. 18 3.13 ac 97 reset modes ......................................................................................... 19 3.13.1 cold ac 97 reset ................................................................................. 19 3.13.2 warm ac 97 reset ............................................................................... 19 3.13.3 register ac 97 reset ........................................................................... 19 3.13.4 new warm ac 97 reset ...................................................................... 19 3.14 ac-link protocol violation - loss of sync ...................................................... 19 4. register interface .......................................................................................... 20 4.1 reset register (index 00h) ................................................................................ 21 4.2 master/headphone volume register (index 02h-04h) ...................................... 21 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ microsoft is a registered trademark of microsoft corporation in the united states and/or other countries. intel is a registered trademark of intel corporation. crystalclear is a registered trademark of cirrus logic. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provid e d as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, trademarks, or t rade secrets. no part of this publi- cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechan ical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by t he user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any mea ns (electronic, mechanical, photo- graphic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be u sed as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a li st of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4201 ds483pp2 3 4.3 mono volume register (index 06h) ................................................................... 22 4.4 pc_beep volume register (index 0ah) ........................................................... 22 4.5 phone volume register (index 0ch) .................................................................. 22 4.6 microphone volume register (index 0eh) .......................................................... 23 4.7 stereo analog mixer input gain registers (indexs 10h - 18h) .......................... 24 4.8 input mux select register (index 1ah) ............................................................... 25 4.9 record gain register (index 1ch) ..................................................................... 25 4.10 general purpose register (index 20h) ............................................................. 26 4.11 3d control register (index 22h) ....................................................................... 26 4.12 powerdown control/status register (index 26h) ............................................. 27 4.13 extended audio id register (index 28h) .......................................................... 28 4.14 extended audio status/control register (index 2ah) ...................................... 28 4.15 pcm dac rate register (index 2ch) ........................................................... 29 4.16 pcm adc rate register (index 32h) ............................................................... 29 4.17 extended modem id register (index 3ch) ...................................................... 30 4.18 extended modem status/control register (index 3eh) ................................... 30 4.19 gpio pin configuration register (index 4ch) .................................................. 30 4.20 gpio pin polarity/type configuration register (index 4eh) ............................ 31 4.21 gpio pin sticky register (index 50h) .............................................................. 31 4.22 gpio pin wakeup mask register (index 52h) ................................................. 32 4.23 gpio pin status register (index 54h) .............................................................. 32 4.24 ac mode control register (index 5eh) ............................................................ 33 4.25 misc. crystal control register (index 60h) ....................................................... 34 4.26 s/pdif control register (index 68h) ................................................................ 35 4.27 serial port control register (index 6ah) .......................................................... 36 4.28 vendor id1 register (index 7ch) ..................................................................... 36 4.29 vendor id2 register (index 7eh) ..................................................................... 37 5. power management ......................................................................................... 38 6. analog hardware description .................................................................. 40 6.1 analog inputs ..................................................................................................... 40 6.1.1 line-level inputs ..................................................................................... 40 6.1.2 cd input .................................................................................................. 40 6.1.3 microphone inputs ................................................................................... 41 6.1.4 pc beep input ......................................................................................... 41 6.1.5 phone input ............................................................................................. 41 6.2 analog outputs .................................................................................................. 42 6.2.1 stereo outputs ........................................................................................ 42 6.2.2 mono output ........................................................................................... 42 6.3 miscellaneous analog signals ........................................................................... 42 6.4 power supplies .................................................................................................. 43 6.5 reference design .............................................................................................. 43 7. sony/philips digital interface (s/pdif) .................................................... 45 8. clocking .............................................................................................................. 46 8.1 pll operation (external clock) ......................................................................... 46 8.2 24.576 mhz crystal operation ........................................................................... 46 9. serial data ports ............................................................................................ 48 9.1 overview ............................................................................................................ 48 9.2 serial data formats ........................................................................................... 48 10. exclusive functions ....................................................................................... 51 11. grounding and layout ................................................................................... 51 12. pin descriptions ............................................................................................... 53 13. parameter and term definitions ............................................................... 59 14. references ......................................................................................................... 61
cs4201 4 ds483pp2 15. package dimensions ........................................................................................ 62 list of figures figure 1. power up timing...................................................................................................... ...... 10 figure 2. codec ready from startup or fault condition ............................................................... 10 figure 3. clocks ............................................................................................................... ............. 10 figure 4. data setup and hold.................................................................................................. .... 11 figure 5. pr4 powerdown and warm reset ................................................................................ 11 figure 6. test mode ............................................................................................................ .......... 11 figure 7. ac-link connections.................................................................................................. ..... 12 figure 8. mixer diagram........................................................................................................ ........ 14 figure 9. ac-link input and output framing.................................................................................. 15 figure 10. line input (replicate for video and aux) .................................................................... 41 figure 11. differential 2 v rms cd input ........................................................................................ 41 figure 12. differential 1 v rms cd input ........................................................................................ 41 figure 13. microphone input .................................................................................................... ..... 42 figure 14. pc_beep input....................................................................................................... ..... 42 figure 15. modem connection .................................................................................................... .. 42 figure 16. line out and headphone out setup............................................................................ 43 figure 17. line out/headphone out setup................................................................................... 43 figure 18. +5v analog voltage regulator..................................................................................... 44 figure 19. cs4201 reference design .......................................................................................... 45 figure 20. consumer and optical s/pdif outputs ....................................................................... 46 figure 21. pll external loop filter............................................................................................ ... 48 figure 22. external crystal.................................................................................................... ........ 48 figure 23. serial data port connection diagram .......................................................................... 51 figure 28. conceptual layout for the cs4201 .............................................................................. 53 figure 24. serial data format 0 (i2s) .......................................................................................... .54 figure 25. serial data format 1 (left justified) ............................................................................ 54 figure 26. serial data format 2 (right justified, 20-bit data) ....................................................... 54 figure 27. serial data format 3 (right justified, 16-bit data) ....................................................... 54 list of tables table 1. register overview..................................................................................................... ...... 20 table 2. analog mixer output attenuation .................................................................................... 21 table 3. microphone input gain values........................................................................................ 23 table 4. analog mixer input gain values...................................................................................... 24 table 5. stereo volume register index ........................................................................................ 24 table 6. input mux selection................................................................................................... ...... 25 table 7. standard sample rates ................................................................................................. .29 table 8. gpio input/output configurations .................................................................................. 31 table 9. slot assignments ..................................................................................................... ...... 33 table 10. serial data format selection ........................................................................................ 3 6 table 11. device id with corresponding part number ................................................................. 37 table 12. powerdown pr bit functions........................................................................................ 38 table 13. powerdown pr function matrix.................................................................................... 39 table 14. power consumption by powerdown mode ................................................................... 39 table 15. clocking configurations .............................................................................................. .. 47 table 16. serial data formats and compatible dacs................................................................. 48
cs4201 ds483pp2 5 1. characteristics and specifications analog characteristics standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v 5%, dvdd = 3.3 v 5%; 1 khz input sine wave; sample frequency, fs = 48 khz; z al =100 k w/ 1000 pf load for mono and line outputs; z al =32 w/ 200 pf load for headphone outputs; c dl = 18 pf load (note 1); measurement bandwidth is 20 hz - 20 khz, 18-bit linear coding for adc functions, 20-bit linear coding for dac functions; mixer registers set for unity gain. notes: 1. z al refers to the analog output pin loading and c dl refers to the digital output pin loading. 2. parameter definitions are given in section 13 , parameter and term definitions . 3. path refers to the signal path used to generate this data. these paths are defined in section 13 , parameter and term definitions . 4. this specification is guaranteed by silicon characterization; it is not production tested. parameter (note 2) symbol path (note 3) CS4201-KQ cs4201-jq unit min typ max min typ max full scale input voltage line inputs mic inputs (20 db = 0) mic inputs (20 db = 1) a-d a-d a-d 0.91 0.91 0.091 1.00 1.00 0.10 - - - 0.91 0.91 0.091 1.00 1.00 0.10 - - - v rms v rms v rms full scale output voltage line and mono outputs headphone output d-a d-a 0.91 - 1.0 1.4 1.13 - 0.91 - 1.0 1.4 1.13 - v rms v rms frequency response (note 4) analog ac = 0.5 db dac ac = 0.5 db adc ac = 0.5 db fr a-a d-a a-d 20 20 20 - - - 20,000 20,000 20,000 20 20 20 - - - 20,000 20,000 20,000 hz hz hz dynamic range stereo analog inputs to line_out mono analog inputs to line_out dac dynamic range adc dynamic range dr a-a a-a d-a a-d 90 85 85 85 95 90 90 90 - - - - - - - - 90 85 87 85 - - - - db fs a db fs a db fs a db fs a dac snr (-20 db fs input w/ ccir-rms filter on output) snr d-a-70---- db total harmonic distortion + noise (-3 db fs input signal): line output headphone output line adc (all inputs) thd+n a-a a-a d-a a-d - - - - -90 -75 -87 -84 -80 - -80 -80 - - - - - - - - -74 -70 -74 -74 db fs db fs db fs db fs power supply rejection ratio (1 khz, 0.5 v rms w/ 5 v dc offset)(note 4) 40 60 - - 40 - db interchannel isolation 70 87 - - 87 - db spurious tone (note 4) - -100 - - -100 - db fs input impedance (note 4) 10 - - 10 - - k w
cs4201 6 ds483pp2 analog characteristics (continued) mixer characteristics (for cs4201 -kq only) absolute maximum ratings (avss1 = avss2 = dvss1 = dvss2 = 0 v) recommended operating conditions (avss1 = avss2 = dvss1 = dvss2 = 0 v) parameter (note 2) symbol path (note 3) CS4201-KQ cs4201-jq unit min typ max min typ max external load impedance line output headphone output 10 32 - - - - 10 32 - - - - k w w output impedance line output headphone output (note 4) - - 730 0.8 - - - - 730 0.8 - - w w input capacitance (note 4) - 5 - - 5 - pf vrefout 2.2 2.4 2.5 2.2 2.4 2.5 v parameter min typ max unit mixer gain range span pc beep line in, aux, cd, video, mic1, mic2, phone mono out, line out, headphone out adc gain - - - - 45.0 46.5 46.5 22.5 - - - - db db db db step size all volume controls except pc beep pc beep - - 1.5 3.0 - - db db parameter min typ max unit power supplies +3.3 v digital +5 v digital analog -0.3 -0.3 -0.3 - - - 6.0 6.0 6.0 v v v total power dissipation (supplies, inputs, outputs) - - 1.25 w input current per pin (except supply pins) -10 - 10 ma output current per pin (except supply pins) -15 - 15 ma analog input voltage -0.3 - avdd+ 0.3 v digital input voltage -0.3 - dvdd + 0.3 v ambient temperature (power applied) -55 - 110 c storage temperature -65 - 150 c parameter symbol min typ max unit power supplies +3.3 v digital +5 v digital analog dvdd1, dvdd2 dvdd1, dvdd2 avdd1, avdd2 3.135 4.75 4.75 3.3 5 5 3.465 5.25 5.25 v v v operating ambient temperature 0 - 70 c
cs4201 ds483pp2 7 digital characteristics (avss = dvss = 0 v) parameter symbol min typ max unit dvdd = 3.3v low level input voltage v il --0.8v high level input voltage v ih 2.15 - - v high level output voltage v oh 3.0 3.25 - v low level output voltage v ol -0.03.35v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current bit_clk, spdif_out sdata_in, eapd - - 24 4 - - ma ma dvdd = 5.0 v low level input voltage v il --0.8v high level input voltage v ih 3.25 - - v high level output voltage v oh 4.5 4.95 - v low level output voltage v ol -0.03.35v input leakage current (ac-link inputs) -10 - 10 a output leakage current (tri-stated ac-link outputs) -10 - 10 a output buffer drive current bit_clk, spdif_out sdata_in, eapd (note 4) - - 24 4 - - ma ma
cs4201 8 ds483pp2 ac 97 serial port timing standard test conditions unless otherwise noted: t ambient = 25 c, avdd = 5.0 v, dvdd = 3.3 v; c l = 55 pf load. parameter symbol min typ max unit reset timing reset# active low pulse width t rst_low 1.0 - - m s reset# inactive to bit_clk start-up delay (xtl mode) (osc mode) (pll mode) t rst2clk - - - 4.0 4.0 2.5 - - - m s m s ms 1st sync active to codec ready set t sync2crd - 62.5 - m s vdd stable to reset# inactive t vdd2rst# tbd clocks bit_clk frequency f clk - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter (depends on xtl_in source) - - 750 ps bit_clk high pulse width t clk_high 36 40.7 45 ns bit_clk low pulse width t clk_low 36 40.7 45 ns sync frequency f sync -48-khz sync period t sync_period - 20.8 - m s sync high pulse width t sync_high -1.3- m s sync low pulse width t sync_low - 19.5 - m s data setup and hold output propagation delay from rising edge of bit_clk t co -68ns input setup time from falling edge of bit_clk t isetup 10 - - ns input hold time from falling edge of bit_clk t ihold 0- -ns input signal rise time t irise 2-6ns input signal fall time t ifall 2-6ns output signal rise time (note 4) t orise 246ns output signal fall time (note 4) t ofall 246ns misc. timing parameters end of slot 2 to bit_clk, sdata_in low (pr4) t s2_pdown 162.8 285 - ns sync pulse width (pr4) warm reset t sync_pr4 1.0 - - m s sync inactive (pr4) to bit_clk start-up delay t sync2clk 162.8 285 - ns setup to trailing edge of reset# (ate test mode) (note 4) t setup2rst 15 - - ns rising edge of reset# to hi-z delay (note 4) t off - - 25 ns
cs4201 ds483pp2 9 bit_clk t rst_low t rst2clk t vdd2rst# vdd reset# figure 1. power up timing figure 2. codec ready from startup or fault condition bit_clk t sync2crd codec_ready sync figure 3. clocks bit_clk sync t irise t ifall t orise t ifall t clk_high t clk_low t sync_high t sync_low t sync_period t clk_period
cs4201 10 ds483pp2 bit_clk t isetup t ihold t co sdata_out, sync sdata_in figure 4. data setup and hold bit_clk t s2_pdown sdata_in sdata_out sync write to 0x20 data pr4 don't care slot 1 slot 2 sync_pr4 sync2clk t t figure 5. pr4 powerdown and warm reset reset# sdata_out, sync t setup2rst sdata_in, t off bit_clk hi-z figure 6. test mode
cs4201 ds483pp2 11 2. general description the cs4201 is a mixed-signal serial audio codec with integrated headphone power amplifier com- pliant to the intel document audio codec 97 specification , revision 2.1 [6] (referred to as ac 97). it is designed to be paired with a digital controller interface, typically located on the pci bus or integrated within the system chip set. the controller is responsible for all communications be- tween the cs4201 and the remainder of the system. the cs4201 contains two distinct functional sec- tions: digital and analog. the digital section in- cludes the ac-link interface, s/pdif interface, se rial data port, power management support, gpio, and sample rate converters (srcs). the analog section includes the analog input multiplexer (mux), stereo output mixer, mono output mixer, headphone amplifier, stereo analog-to-digital converters (adcs), stereo digital-to-analog converters (dacs), and their associated volume contro ls. 2.1 ac-link all communication with the cs4201 is established with a 5-wire digital interface to the controller, as shown in figure 7. this interface is called the ac-link. all clocking for the serial communication is synchronous to the bit_clk signal. bit_clk is gene rated by the primary audio codec and is used to clock the controller and any secondary audio co- decs. both input and output ac-link audio frames are organized as a sequence of 256 serial bits form- ing 13 groups referred to as slots. during each au- dio frame, data is passed bi-directionally between the cs4201 and the controller. the input frame is driven from the cs4201 on the sdata_in line. the output frame is driven from the controller on the sdata_out line. the controller is also re- sponsible for issuing reset commands via the re- set# signal. after being reset, the cs4201 is responsible for notifying the controller that it is ready for operation after synchronizing its internal functions. the cs4201 ac-link signals must use the same digital supply voltage as the controller chip, ei- ther +5 v or +3.3 v. see section 3, ac-link frame definition , for detailed ac-link informati on. codec sync bit_clk sdata_out sdata_in reset# digital ac'97 controller figure 7. ac-link connections
cs4201 12 ds483pp2 2.2 control registers the cs4201 contains a set of ac 97 compliant control registers, as well as a set of cirrus defined control registers. these registers control the basic functions and features of the cs4201. read access- es of the control registers by the ac 97 controller are accomplished with the requested register index in slot 1 of a sdata_out frame. the following sdata_in frame will contain the read data in its slot 2. write operations are similar, with the regis- ter index in slot 1 and the write data in slot 2 of a sdata_out frame. the function of each input and output frame is detailed in section 3, ac-link frame definition . individual register descriptions are found in section 4, register interface . 2.3 sample rate converters the sample rate converters (src) provide high ac- curacy digital filters supporting sample frequencies other than 48 khz to be captured from the cs4201 or played from the controller. ac 97 requires sup- port for 2 audio rates (44.1 and 48 khz). in addi- tion, the intel ? i/o controller hub (ichx) specification [8] requires support for 5 more audio rates (8, 11.025, 16, 22.05, and 32 khz). the cs4201 supports all these rates, as shown in table 7. 2.4 output mixers the cs4201 has two output mixers, illustrated in figure 8. the stereo output mixer sums together the analog inputs to the cs4201, including the pc_beep and phone signals, according to the settings in the volume control registers. the stereo output mix is then sent to the line_out and hp_out pins of the cs4201. the mono output mixer generates a monophonic sum of the left and right channels from the stereo input mixer. the mono output mix is then sent to the mono_out pin on the cs4201. 2.5 input mux the input multiplexer controls which analog input is sent to the adcs. the output of the input mux is converted to stereo 18-bit digital pcm data and sent to the controller chip via the ac-link sdata_in signal. 2.6 volume control the cs4201 volume registers control analog input levels to the input mixer and analog output vol- umes, including the master volume level, and the headphone volume level. the pc_beep volume control uses 3 db steps with a range from 0 db to -45 db of attenuation. all other analog volume controls use 1.5 db steps. the analog inputs have a mixing range of +12 db of signal gain to -34.5 db of signal attenuation. the analog output volume controls have from 0 db to -46.5 db of attenuation for line_out, hp_out and mono_out.
cs4201 ds483pp2 13 vol mute vol mute vol mute vol vol mute vol vol vol mute boost s s s 1/2 output buffer headphone amplifier output buffer vol vol adc input mux vol adc mute pcm_out pc_beep phone mic1 mic2 line cd video aux analog stereo input mixer analog stereo output mixer master volume headphone volume mono volume mono out select stereo to mono mixer main adc gain main a/d converters mic select mono out line out pcm_in dac main d/a converters s 1/2 stereo to mono mixer mute mute mute 3d headphone out s 3d output mixer vol mute mute mute pcm out path dac direct mode pc beep bypass figure 8. mixer diagram
cs4201 14 ds483pp2 3. ac-link frame definition the ac-link is a bi-directional serial port with data organized into frames consisting of one 16-bit and twelve 20-bit time-division multiplexed slots. the first slot, called the tag slot, contains bits indicating if the cs4201 is ready to receive data (input frame) and which, if any, other slots contain valid data. slots 1 through 12 contain audio or control/status data. both the serial data output and input frames are defined from the controller perspective, not from the cs4201 perspective. the controller synchronizes the beginning of a frame with the sync signal. figure 9 shows the position of each bit location within the frame. the first bit position in a new serial data frame is f0 and the last bit position in the serial data frame is f255. when sync goes active (high) and is sampled ac- tive by the cs4201 (on the falling edge of bit_clk), both devices are synchronized to a new serial data frame. the data on the sdata_out pin at this clock edge is the final bit of the previous frames serial data. on the next rising edge of bit_clk, the first bit of slot 0 is driven by the controller on the sdata_out pin. on the next falling edge of bit_clk, the cs4201 latches this data in, as the first bit of the frame. 20.8 m s (48 khz) tag phase data phase 12.288 mhz 81.4 ns sync bit_clk sdata_out sdata_in f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 d19 f255 valid frame slot 1 valid 0 r/w 0 wd15 f36 f57 d19 d18 d19 d19 d18 d19 rd15 0 0 0 0 f0 f1 f2 f16 f15 f14 f13 f12 f35 f56 f76 f255 f36 f57 f255 f255 0 0 gpio int f96 f96 d19 slot 0 slot 1 slot 2 slot 3 slot 4 slots 5-12 slot 2 valid slot 1 valid slot 2 valid codec ready 0 slot 12 valid codec id1 codec id0 slot 12 valid gpio int bit frame position: bit frame position: figure 9. ac-link input and output framing
cs4201 ds483pp2 15 3.1 ac-link serial data output frame in the serial data output frame, data is passed on the sdata_out pin to the cs4201 from the controller. figure 9 illustrates the serial port timing. the pcm playback data being passed to the cs4201 is shifted out msb first in the most significant bits of each slot. any pcm data from the ac 97 controller that is not 20 bits wide should be left justified in its corresponding slot and dithered or zero-padded in the unused bit positions. bits that are reserved should always be cleared by the ac 97 controller. 3.1.1 serial data output slot tags (slot 0) valid frame determines if any of the following slots contain either valid playback data for the cs4201 dacs or data for read/write operations. when set, at least one of the other ac-link slots con- tain valid data. if this bit is clear, the remainder of the frame is ignored. slot [1:2] valid indicates the validity of data in their corresponding serial data output slots. if a bit is set, the corresponding output slot contains valid data. if a bit is cleared, the corresponding slot will be ignored. slot [3:11] valid indicates slot [3:11] contains valid playback data for the cs4201. if a slot valid bit is set, the named slot contains valid audio data. if the bit is clear, the slot will be ignored. the cs4201 supports alternate slot mapping as defined in the ac 97 2.1 specification. for more informa- tion, see section 4.24, ac mode control register (index 5eh) . slot 12 valid indicates slot 12 contains valid gpio control data. codec id[1:0] codec id of the audio codec being accessed during this current ac-link frame. codec id[1:0] = 00 indicates the primary codec is being accessed. codec id[1:0] = 01, 10, or 11 in- dicates one of three possible secondary codecs is being accessed. a non-zero value of one or more of the codec id bits indicates a valid read or write address in slot 1, and the slot 1 r/w bit indicates presence or absence of valid data in slot 2. 3.1.2 command address port (slot 1) r/w read/write . when this bit is set, a read of the ac 97 register specified by the register index bits will occur in the primary ac 97 2.1 audio codec. when the bit is cleared, a write will oc- cur. for any read or write access to occur, the frame valid bit (f0) must be set and the co- dec id in bits f[14:15] must match the codec id of the ac 97 2.1 audio codec being accessed. additionally, for a primary codec, the slot 1 valid bit (f1) must be set for a read access and both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be set for a write access. for a secondary codec, both the slot 1 valid bit (f1) and the slot 2 valid bit (f2) must be cleared for read and write accesses. ri[6:0] register index/address. bits ri[6:0] contain the 7-bit register index to the ac 97 registers in the cs4201. all registers are defined at word addressable boundaries. ri0 must be cleared to access cs4201 registers. bit 1514131211109876543210 valid frame slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid slot 9 valid slot 10 valid slot 11 valid slot 12 valid reserv ed codec id1 codec id0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w ri6 ri5 ri4 ri3 ri2 ri1 ri0 reserved
cs4201 16 ds483pp2 3.1.3 command data port (slot 2) wd[15:0] bits wd[15:0] contain the 16-bit value to be written to the register. if an access is a read, this slot is ignored. note: for any write to an ac 97 register, the write is defined to be an atomic access. this means that when the slot valid bit for slot 1 is set, the slot valid bit for slot 2 should always be set during the same audio frame. no write access may be split across 2 frames. 3.1.4 pcm playback data (slots 3-11) pd[19:0] 20-bit pcm playback (2s complement) data for the left and right dacs and/or the s/pdif transmitter. table 9 lists a cross reference for each function and its respective slot. the map- ping of a given slot to a dac is determined by the state of the id[1:0] bits found in the extend- ed audio id register (index 28h) and by the sm[1:0] and amap bits found in the ac mode control register (index 5eh) . 3.1.5 gpio data (slot12) gpio[1:0] gpio pin control bits. these bits control the gpio pins on the cs4201 which are configured as outputs. write accesses using gpio pin control bits configured as outputs will be reflected on the gpio pin output on the next ac-link frame. write accesses using gpio pin control bits configured as inputs will have no effect and are ignored. if the gpoc bit in the misc. crystal control register (index 60h) is set, the bits in output slot 12 are ignored and gpio pins con- figured as outputs are controlled through the gpio pin status register (index 54h) . bit 19181716151413121110987654 3210 wd15 wd14 wd13 wd12 wd11 wd10 wd9 wd8 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 reserved bit 191817161514131211109876543210 pd19 pd18 pd17 pd16 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 not implemented gpio1 gpio0 reserved
cs4201 ds483pp2 17 3.2 ac-link serial data input frame in the serial data input frame, data is passed on the sdata_in pin from the cs4201 to the ac 97 con- troller. the data format for the input frame is very similar to the output frame. figure 9 illustrates the serial port timing. the pcm capture data from the cs4201 is shifted out msb first in the most significant 18 bits of each slot. the least significant 2 bits in each slot will be cleared. if the host requests pcm data from the ac 97 controller that is less than 18 bits wide, the controller should dither and round or just round (but not trun- cate) to the desired bit depth. bits that are reserved or not implemented in the cs4201 will always be returned cleared. 3.2.1 serial data input slot tag bits (slot 0) codec ready indicates the readiness of the cs4201 ac-link and control and status registers. immediately after a cold reset this bit will be clear. once the cs4201 clocks and voltages are stable, this bit will be set. until the codec ready bit is set, no ac-link transactions should be at- tempted by the controller. the codec ready bit does not indicate readiness of the dacs, adcs, vref, or any other analog function. those must be checked in the powerdown con- trol/status register (index 26h) by the controller before any access is made to the mixer reg- isters. any accesses to the cs4201 while codec ready is cleared are ignored. slot 1 valid indicates slot 1 contains a valid read back address. slot 2 valid indicates slot 2 contains valid register read data. slot [3:8] valid indicates slot [3:8] contains valid capture data from the cs4201 adc. if a bit is set the cor- responding input slot contains valid data. slot 12 valid indicated slot 12 contains valid gpio status data. 3.2.2 status address port (slot 1) ri[6:0] register index. the read-back address port echoes the ac 97 register address when a reg- ister read has been requested in the previous frame. the cs4201 will only echo the register index for a read access. write accesses will not return valid data in slot 1. sr[3:9,11] slot request for slots 3 - 9 and 11. if srx is set, this indicates the cs4201 src does not need a new sample on the next ac-link frame for that particular slot. if srx is cleared, the src indicates a new sample is needed on the following frame. if the vra bit in the extended audio status/control register (index 2ah) is cleared, the sr bits are always 0. when vra is set, the srcs are enabled and the sr bits are used to request data. bit 1514131211109876543210 codec ready slot 1 valid slot 2 valid slot 3 valid slot 4 valid slot 5 valid slot 6 valid slot 7 valid slot 8 valid 000 slot 12 valid reserved bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res ri6 ri5 ri4 ri3 ri2 ri1 ri0 sr3 sr4 sr5 sr6 sr7 sr8 sr9 0 sr11 0 reserved
cs4201 18 ds483pp2 3.2.3 status data port (slot 2) rd[15:0] 16-bit register value. the read-back data port contains the register data requested by the controller from the previous read request. all read requests will return the read address in the read-back address port (slot 1) and the register data in the read-back data port (slot 2) on the following serial data frame. 3.2.4 pcm capture data (slot 3-8) cd[17:0] 18-bit pcm (2s complement) data. the mapping of a given slot to an adc is determined by the state of the id[1:0] bits found in the extended audio id register (index 28h) and the sm[1:0] and amap bits found in the ac mode control register (index 5eh) . the definition of each slot can be found in table 9. the capture data in slot [3:8] will only be valid when the respective slot valid bit is set in slot 0. 3.2.5 gpio pin status (slot 12) gpio[1:0] status of the gpio[1:0] pins. if the pin is configured as an input, the gpio pin status will be reflected on slot 12 of the sdata_in stream. if the pin is configured as an output, the output pin status, which is controlled by the gpio pin control bit in the sdata_out stream, will be reflected back on the gpio pin status bit of the sdata_in stream in the next frame. gpio_int this bit indicates that a gpio interrupt event has occurred. the occurrence of this interrupt is determined by the gpio interrupt requirements as outlined in the gpio pin wakeup mask register (index 52h) description. the gpio_int bit is cleared by writing a 0 to the gpio pin status bit corresponding to the gpio pin which generated the interrupt. bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 reserved bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cd17 cd16 cd15 cd14 cd13 cd12 cd11 cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 0 0 bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0000000000000gpio1gpio0reserved gpio _int
cs4201 ds483pp2 19 3.3 ac 97 reset modes t he cs4201 supports four reset methods, as defined in the ac 97 specification: cold ac 97 reset , warm ac 97 reset , register ac 97 reset, and new warm ac 97 reset . a cold reset results in all ac 97 logic (registers included) initialized to its default state. a warm reset leaves the contents of the ac 97 register set unaltered. a register reset initializes only the ac 97 registers to their default states. ac 97 2.1 additionally defines a so-called new warm reset, a warm reset variation. the tim- ing of power-up/reset events is discussed in detail in section 5, power management . 3.3.1 cold ac 97 reset a cold reset is achieved by asserting reset# for a minimum of 1 s after the power supply rails have stabilized. this is done in accordance with the min- imum timing specifications in the ac 97 serial port timing section. once de-asserted, all of the cs4201 registers will be reset to their default pow- er-on states and the bit_clk and sdata_in sig- nals will be reactivate d. 3.3.2 warm ac 97 reset a warm reset allows the ac-link to be reactivated without losing information in the cs4201 registers. warm reset is the required resume sequence to re- cover from a d3 hot state where the ac-link had been halted yet full power had been maintained. a prima- ry codec warm reset is initiated when the sync signal is driven high for at least 1 s and then driven low in the absence of the bit_clk clock signal. the bit_clk clock will not restart until at least 2 normal bit_clk clock periods (162.8 ns) after the sync signal is de-asserted. a secondary codec warm reset is recognized when the primary codec on the ac-link resumes bit_clk generation. the cs4201 will wait for bit_clk to be stable and then restore sdata_in activity and s/pdif and/or seri- al data port transmission on the following frame. 3.3.3 register ac 97 reset t he third reset mode provides a register reset to the cs4201. this is available only when the cs4201 ac-link is active and the codec ready bit is set. the audio (including extended audio) registers ( in- dex 00h - 38h ) and the vendor specific registers ( in- dex 5ah - 7ah ) are reset to their default states by a write of any value to the reset register (index 00h) . the modem (including gpio) registers ( index 3ch - 56h ) are reset to their default states by a write of any value to the extended modem id register (index 3ch) . 3.3.4 new warm ac 97 reset t he new warm reset also allows the ac-link to be reactivated without losing information in the regis- ters. new warm reset is the required resume se- quence to recover from a d3 cold state where ac-link power has been removed. new warm re- set is recognized by the low-high transition of re- set# after the ac-link has been programmed into pr4 powerdown. the new warm reset functional- ity can be disabled by setting the crst bit in the misc. crystal control register (index 60h) . 3.4 ac-link protocol violation - loss of sync the cs4201 is designed to handle sync protocol violations. the following are situations where the sync protocol has been violated: ? the sync signal is not sampled high for exact- ly 16 bit_clk clock cycles at the start of an audio frame. ? the sync signal is not sampled high on the 256th bit_clk clock period after the previous sync assertion. ? the sync signal goes active high before the 256th bit_clk clock period after the previous sync assertion. upon loss of synchronization with the controller, the cs4201 will mute all analog outputs and clear the codec ready bit in the serial data input frame until two valid frames are detected. during this de- tection period, the cs4201 will ignore all register reads and writes and will discontinue the transmis- sion of pcm capture data.
cs4201 20 ds483pp2 4. register interface reg register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset 0 se4 se3 se2 se1 se0 0 id8 id7 0 0 id4 0 0 0 0 1990h 02h master volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 04h headphone volume mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4 mr3 mr2 mr1 mr0 8000h 06h mono volume mute 0 0 0 0 0 0 0 0 0 mm5 mm4 mm3 mm2 mm1 mm0 8000h 0ah pc_beep volume mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 0000h 0ch phone volume mute 0 0 0 0 0 0 0 0 0 0 gn4 gn3 gn2 gn1 gn0 8008h 0eh mic volume mute 0 0 0 0 0 0 0 0 20db 0 gn4 gn3 gn2 gn1 gn0 8008h 10h line in volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 12h cd volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 14h video volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 16h aux volume mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 18h pcm out vol mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 8808h 1ah record select 0 0 0 0 0 sl2 sl1 sl0 0 0 0 0 0 sr2 sr1 sr0 0000h 1ch record gain mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0 8000h 20h general purpose pop 0 3d 0 0 0 mix ms lpbk 0 0 0 0 0 0 0 0000h 22h 3d control 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 0000h 26h powerdown ctrl/stat eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc 000fh 28h extd audio id id1 id0 0 0 0 0 amap 0 0 0 0 0 0 0 0 vra x201h 2ah extd audio stat/ctrl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vra 0000h 2ch pcm front dac rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 32h pcm l/r adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 bb80h 3ch extd modem id id1 id0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x000h 3eh extd modem stat/ctrl 0000000pra0 0000 0 0 gpio 0100h 4ch gpio pin configuration 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gc1 gc0 0003h 4eh gpio pin polarity/type 1 1 1 1 1 1 1 1 1 1 1 1 1 1 gp1 gp0 ffffh 50h gpio pin sticky 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gs1 gs0 0000h 52h gpio pin wakeup mask 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gw1 gw0 0000h 54h gpio pin status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gi1 gi0 0000h cirrus defined registers : 5eh ac mode control 0 0 0 0 aspm 0 0 ddm amap spas sm1 sm0 0 0 0 0 0080h 60h misc. crystal control 0 0 0 dpc 0 0 reserved 10db crst reserved gpoc reserved 0 0002h 68h s/pdif control spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro 0000h 6ah serial port control sden 000 0 0 0 0 0 0 00 s2en sdsc sdf1 sdf0 0000h 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4352h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 1 rev2 rev1 rev0 5949h table 1. register overview
cs4201 ds483pp2 21 4.1 reset register (index 00h) se[4:0] 3d stereo enhancement technique. 00110 - crystal 3d stereo enhancement. id8 id8 = 1, 18-bit adc resolution. id7 id7 = 1, 20-bit dac resolution. id4 headphone out support. the state of this bit depends on the state of the hpcfg pin. default 1990h, read-only data any write to this register causes a register reset to the default state of the audio ( index 00h - 38h ) and vendor specific ( index 5ah - 7ah ) registers. a read from this register returns configuration information about the cs4201. 4.2 master/headphone volume register (index 02h-04h) mute master mute for the line_out_l/r or hp_out_l/r output signals. ml[4:0] volume control for the left channel output signal. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. see table 2 for further gain levels. ml5 setting ml5 sets the left channel attenuation to -46.5 db by forcing ml[4:0] to a 1 state. ml[5:0] will read back 01111 when ml5 has been set. table 2 summarizes this behavior. mr[4:0] volume control for the right channel output signal. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. see table 2 for further gain levels. mr5 setting mr5 sets the right channel attenuation to -46.5 db by forcing mr[4:0] to a 1 state. mr[5:0] will read back 011111 when mr5 has been set. table 2 summarizes this behavior. default 8000h, corresponding to 0 db attenuation and mute on. if the hpcfg pin is left floating, register 02h controls the master volume and register 04h controls the headphone volume. if the hpcfg pin is tied low, register 02h controls the headphone volume and register 04h is a read-only register and always returns 0000h when read. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0se4se3se2se1se00id8id700id40000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 ml5 ml4 ml3 ml2 ml1 ml0 0 0 mr5 mr4mr3mr2mr1mr0 mx5..mx0 write mx5..mx0 read gain level 000000 000000 0 db 000001 000001 -1.5 db ... 011111 011111 -46.5 db 100000 0 11111 -46.5 db ... ... ... 111111 011111 -46.5 db table 2. analog mixer output attenuation
cs4201 22 ds483pp2 4.3 mono volume register (index 06h) mute when set, mutes the mono_out signal. mm[4:0] mono attenuation. least significant bit represents -1.5 db with 00000 = 0 db. the total range is 0 db to -46.5 db. see table 2 for further gain levels. mm5 setting mm5 sets the mono attenuation to -46.5 db by forcing mm[4:0] to a 1 state. mm[5:0] will read back 011111 when mm5 has been set. table 2 summarizes this behavior. default 8000h, corresponding to 0 db attenuation and mute set. 4.4 pc_beep volume register (index 0ah) mute when set, mutes the pc_beep signal. pv[3:0] volume control for the pc_beep pin. least significant bit represents -3 db with 0000 = 0 db. the total range is 0 db to -45 db. default 0000h, unmuted, with 0 db attenuation after the cs4201 is removed from the reset state. 4.5 phone volume register (index 0ch) mute when set, mutes the phone signal. gn[4:0] phone volume control. least significant bit represents -1.5 db with 01000 = 0 db. the total range is +12 db to -34.5 db. see table 4 for further gain levels. default 8008h, 0 db attenuation and mute set. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute000000000mm5 mm4 mm3 mm2 mm1 mm0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 0 0 0 0 0 0 0 pv3 pv2 pv1 pv0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute0000000000gn4gn3gn2gn1gn0
cs4201 ds483pp2 23 4.6 microphone volume register (index 0eh) mute when set, mutes mic1/mic2 signal. gn[4:0] mic1/mic2 volume control. least significant bit represents -1.5 db with 01000 = 0 db. the total range is +12 db to -34.5 db. see table 3 for further gain levels. 20db enables 20 db microphone boost block. in combination with the 10db boost bit in the misc. crystal control register (index 60h) this bit allows for variable boost from 0 db to +30 db. table 3 summarizes this behavior. default 8008h, 0 db attenuation and mute set. this register controls the gain level of the microphone input source to the input mixer. it also controls the +20 db gain block which connects to the input volume control and to the input record mux. the selection of mic1 or mic2 input pins is controlled by the ms bit in the general purpose register (index 20h) . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute0000000020db0gn4gn3gn2gn1gn0 gn4 - gn0 gain level 10db = 0 20db = 0 10db = 1 20db = 0 10db = 0 20db = 1 10db = 1 20db = 1 00000 +12.0 db +22.0 db +32.0 db +42.0 db 00001 +10.5 db +20.5 db +30.5 db +40.5 db ... ... ... 00111 +1.5 db +11.5 db +21.5 db +31.5 db 01000 0.0 db +10.0 db +20.0 db +30.0 db 01001 -1.5 db +8.5 db +18.5 db +28.5 db ... ... ... 11111 -34.5 db -24.5 db -14.5 db -4.5 db table 3. microphone input gain values
cs4201 24 ds483pp2 4.7 stereo analog mixer input gain registers (indexs 10h - 18h) mute when set, mutes the respective input signal. setting this bit mutes both right and left inputs. gl[4:0] left volume control. least significant bit represents -1.5 db with 01000 = 0 db. the total range is +12 db to -34.5 db. see table 4 for further gain levels. gr[4:0] right volume control. least significant bit represents -1.5 db with 01000 = 0 db. the total range is +12 db to -34.5 db. see table 4 for further gain levels. default 8808h, 0 db gain with mute enabled. these registers control the gain levels of the analog input sources to the input mixer. the analog inputs associated with stereo analog mixer input gain registers (indexs 10h - 18h) are found in table 5. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 gl4 gl3 gl2 gl1 gl0 0 0 0 gr4 gr3 gr2 gr1 gr0 gn4 - gn0 gain level 00000 +12.0 db 00001 +10.5 db 00111 +1.5 db 01000 0.0 db 01001 -1.5 db 11111 -34.5 db table 4. analog mixer input gain values register index function 10h line in volume 12h cd volume 14h video volume 16h aux volume 18h pcm out volume table 5. stereo volume register index
cs4201 ds483pp2 25 4.8 input mux select register (index 1ah) sl[2:0] left channel adc input source select. sr[2:0] right channel adc input source select. default 0000h, mic inputs selected for both channels. when capturing pcm data, this register controls the input mux for the adcs. table 6 lists the possible values for each input. 4.9 record gain register (index 1ch) mute when set, mutes the input to the adcs. gl[3:0] left adc gain. least significant bit represents +1.5 db with 0000 = 0 db. the total range is 0 db to +22.5 db. gr[3:0] right adc gain. least significant bit represents +1.5 db with 0000 = 0 db. the total range is 0 db to +22.5 db. default 8000h, 0 db gain with mute on. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000sl2sl1sl000000sr2sr1sr0 sx2 - sx0 record source 000 mic 001 cd input 010 video input 011 aux input 100 line input 101 stereo mix 110 mono mix 111 phone input table 6. input mux selection d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute 0 0 0 gl3 gl2 gl1 gl0 0 0 0 0 gr3 gr2 gr1 gr0
cs4201 26 ds483pp2 4.10 general purpose register (index 20h) pop this bit controls the pcm out path. when cleared, the pcm out path is mixed pre 3d. when set, the pcm out path is mixed post 3d. 3d 3d enable. if set, enables the crystalclear tm 3d stereo enhancement. this function is not available in dac direct mode (ddm). mix mono output path. when clear, the mono mix out (a mix of the 4 analog stereo sources plus mic and pcm_out) is selected for mono_out. when set, the mic path is sent to mono out. ms microphone select. determines which of the two mic inputs are passed to the mixer. when set, mic2 input is selected; when clear mic1 is selected. lpbk loopback. if set, enables adc/dac loopback mode. this bit routes the adc output to the dac input without involving the ac-link. default 0000h. 4.11 3d control register (index 22h) s[3:0] spatial enhancement depth control. spatial enhancement is enabled by the 3d bit in the general purpose register (index 20h) . 0000 - minimum spatial enhancement. 1111 - maximum spatial enhancement. default 0000h, minimum spatial enhancement added. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pop03d000mixmslpbk0000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000s3s2s1s0
cs4201 ds483pp2 27 4.12 powerdown control/status register (index 26h) eapd external amplifier power down. the eapd pin follows this bit. generally used to power-down external amplifiers. the eapd bit is mutually exclusive with the sdsc bit in the serial port control register (index 6ah) . the sdsc bit must be cleared before the eapd bit may be set. if the sdsc bit is 1, eapd is a read-only bit and always returns 0. pr6 when set, the headphone amplifier is powered down. pr5 when set, the internal master clock is disabled (bit_clk running). the only way to recover from setting this bit is through a cold ac 97 reset (driving the reset# signal active). pr4 when set, the ac-link is powered down (bit_clk off). the ac-link can be restarted through a warm ac 97 reset using the sync signal, or a cold ac 97 reset using the reset# signal (the primary codec only). pr3 when set, the analog mixer and voltage reference are powered down. when clearing this bit, the anl, adc, and dac bits should be checked before writing any mixer registers. pr2 when set, the analog mixer is powered down (the voltage reference is still active). when clearing this bit, the anl bit should be checked before writing any mixer registers. pr1 when set, the dacs are powered down. when clearing this bit, the dac bit should be checked before sending any data to the dacs. pr0 when set, the adcs and the adc input muxes are powered down. when clearing this bit, no valid data will be sent down the ac-link until the adc bit goes high. ref voltage reference ready status. when set, indicates the voltage reference is at a nominal level. anl analog ready status. when set, the analog output mixer, input multiplexer, and volume con- trols are ready. when clear, no volume control registers should be written. dac dac ready status. when set, the dacs are ready to receive data across the ac-link. when clear, the dacs will not accept any valid data. adc adc ready status. when set, the adcs are ready to send data across the ac-link. when clear, no data will be sent to the controller. default 0000h, all blocks are powered on. the lower four bits will eventually change as the cs4201 finishes an initialization and calibration sequence. the pr[6:0] and the eapd bits are power-down control for different sections of the cs4201 as well as external am- plifiers. the ref, anl, dac, and adc bits are read-only status bits which, when set, indicate that a particular sec- tion of the cs4201 is ready. after the controller receives the codec ready bit in slot 0, these status bits must be checked before writing to any mixer registers. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 0 0 0 0 ref anl dac adc
cs4201 28 ds483pp2 4.13 extended audio id register (index 28h) id[1:0] codec configuration id. primary is 00; secondary is 01,10,or 11. this is a reflection of the id[1:0]# configuration pins. the state of the id[1:0] bits is determined at power-up from the codec id[1:0]# pins and the current clocking scheme, see table 15. amap audio slot mapping. the amap bit indicates whether the optional ac 97 2.1 compliant ac-link slot to audio dac mapping is supported. this bit is a shadow of the amap bit in the ac mode control register (index 5eh) . the pcm playback and capture slots are mapped ac- cording to table 9. vra variable rate pcm audio. the vra bit indicates whether variable rate pcm audio is support- ed. this bit always returns 1, indicating that variable rate pcm audio is available. default x201h. the extended audio id register (index 28h) is a read only register. 4.14 extended audio status/control register (index 2ah) vra enable variable rate audio. when set, this bit allows access to the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) . this bit must be set in order to use variable pcm playback or capture rates. the vra bit also serves as a power- down for the dac and adc src blocks. clearing vra will reset the pcm front dac rate register (index 2ch) and the pcm l/r adc rate register (index 32h) to their default values. the src data path is flushed and the slot request bits for the currently active dac slots will be fixed at 0. default 0000h. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1id00000amap00000000vra d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 000000000000000vra
cs4201 ds483pp2 29 4.15 pcm dac rate register (index 2ch) sr[15:0] dac sample rate select. can only be written when the vra bit of the extended audio sta- tus/control register (index 2ah) is set. if the vra bit is clear, all writes are ignored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vra bit is set, sev- en standard sample rates are available. if a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicat- ed in table 7. all register read transactions will reflect the actual value stored (column 2 in table 7) and not the one attempted to be written. default bb80h, indicating 48 khz sample rate. 4.16 pcm adc rate register (index 32h) sr[15:0] adc sample rate select. can only be written when the vra bit of the extended audio sta- tus/control register (index 2ah) is set. if the vra bit is clear, all writes are ignored and the register reads back bb80h; corresponding to a 48 khz sample rate. if the vra bit is set, sev- en standard sample rates are available. if a sample rate written to the register is not directly supported, the attempted value to be written will be decoded according to the ranges indicat- ed in table 7. all register read transactions will reflect the actual value stored (column 2 in table 7) and not the one attempted to be written. default bb80h, indicating 48 khz sample rate. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sample rate (hz) sr[15:0] sr[15:12] decode range 8,000 1f40 0 or 1 11,025 2b11 2 16,000 3e80 3 22,050 5622 4 or 5 32,000 7d00 6 or 7 44,100 ac44 8,9,ah 48,000 bb80 bh,ch,dh,eh,fh table 7. standard sample rates d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0
cs4201 30 ds483pp2 4.17 extended modem id register (index 3ch) id[1:0] codec configuration id. primary is 00; secondary is 01,10,or 11. this is a reflection of the id[1:0]# configuration pins. the state of the id[1:0] bits is determined at power-up from the codec id[1:0]# pins and the current clocking scheme, see table 15. default x000h. indicating no supported modem functions. the extended modem id is a read/write register that identifies the cs4201 modem capabilities. writing any value to this location issues a reset to modem registers ( index 3ch-54h ), including gpio registers ( index 4ch - 54h ). audio registers are not reset by a write to this location. 4.18 extended modem status/control register (index 3eh) pra gpio power down. when set, the gpio pins are tri-state and powered down. input slot 12 is marked invalid if the ac-link is active. the serial data mode and the gpio mode of oper- ation are mutually exclusive. to use any gpio function, sden of the serial port control reg- ister (index 6ah) must be 0 prior to clearing pra. if the sden bit is 1, pra is a read-only bit and always returns 1. gpio gpio. when set, indicates the gpio subsystem is ready for use. if gpio is set, input slot 12 will also be marked valid. default 0100h 4.19 gpio pin configuration register (index 4ch) gc[1:0] gpio pin configuration. when set, defines the corresponding gpio pin as an input. when clear, defines the corresponding gpio pin as an output. default 0003h after a cold reset, power up, or modem register reset (see extended modem id register (index 3ch) ) all gpio pins are configured as inputs. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1id000000000000000 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0000000pra0000000gpio d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gc1gc0
cs4201 ds483pp2 31 4.20 gpio pin polarity/type configuration register (index 4eh) gp[1:0] gpio pin configuration. the register defines gpio input polarity (0 = low, 1 = high active) when a gpio pin is configured as an input. it defines gpio output type (0 = cmos, 1 = open-drain) when a gpio pin is configured as an output. the gc[1:0] bits in the gpio pin configuration register (index 4ch) define the gpio pins as inputs or outputs. see table 8. default ffffh when the gpio pin is defined as an input, its status is reported in the gpio pin status register (index 54h) as well as input slot 12. 4.21 gpio pin sticky register (index 50h) gs[1:0] gpio pin sticky. the register defines gpio input type (0 = not sticky, 1 = sticky) when a gpio pin is configured as an input. the gpio pin status of an input configured as sticky is cleared by writing a 0 to the corresponding bit of the gpio pin status register (index 54h) , and by reset. default 0000h after a cold reset or a modem register reset, this register defaults to all 0s specifying non-sticky. sticky is defined as edge sensitive, non-sticky as level sensitive. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11111111111111gp1gp0 gcx gpx function configuration 0 0 output cmos drive 0 1 output open drain 1 0 input active low 1 1 input active high (default) table 8. gpio input/output configurations d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gs1gs0
cs4201 32 ds483pp2 4.22 gpio pin wakeup mask register (index 52h) gw[1:0] gpio pin wakeup. the register provides a mask for determining if an input gpio change will generate a wakeup or gpio_int (0 = no, 1 = yes). when the ac-link is powered down ( pow- erdown control/status register (index 26h) bit pr4 = 1 for primary codecs), a wakeup event will trigger the assertion of sdata_in. when the ac-link is powered up, a wakeup event will appear as gpio_int = 1 on bit 0 of input slot 12. default 0000h an ac-link wakeup interrupt is defined as a 0 to 1 transition on sdata_in when the ac-link is powered down ( powerdown control/status register (index 26h) bit pr4 = 1 for primary codecs). gpio bits which have been pro- grammed as inputs, sticky, and wakeup, upon transition either (high-to-low) or (low-to-high) depending on pin po- larity, will cause an ac-link wakeup if and only if the ac-link was powered down. once the controller has re-established communication with the cs4201 following a warm reset, it will continue to signal the wakeup event through the gpio_int bit of input slot 12 until the ac 97 controller clears the interrupt-causing bit in the gpio pin status register (index 54h) ; or the wakeup, config, or sticky status of that gpio pin changes. after a cold reset or a modem register reset (see extended modem id register (index 3ch) ) this register defaults to all 0s, specifying no wakeup event. the upper 14 bits of this register always return 0. 4.23 gpio pin status register (index 54h) gi[1:0] gpio pin status. this register reflects the state of all gpio pin inputs and outputs. these values are also reflected in slot 12 of every sdata_in frame. gpio inputs configured as sticky are cleared by writing a 0 to the corresponding bit of this register. the gpio_int bit in input slot 12 is cleared by clearing all interrupt causing bits in this register. default 0000h, the default value is always the state of the gpio pin. gpio pins which have been programmed as inputs and sticky, upon transition either (high-to-low) or (low-to-high) depending on pin polarity, will cause the individual gi bit to go asserted 1, and remain asserted until a write of 0 to that bit. gpio pins which have been programmed as outputs are controlled either through output slot 12 or through this register, depending on the state of the gpoc bit in the misc. crystal control register (index 60h) . if the gpoc bit is cleared, the gi bits in this register are read-only and reflect the status of the corresponding gpio output pin set through output slot 12. if the gpoc bit is set, the gi bits in this register are read/write bits and control the corresponding gpio output pins. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gw1gw0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00000000000000gi1gi0
cs4201 ds483pp2 33 4.24 ac mode control register (index 5eh) aspm analog s/pdif mode. this bit controls the input source to the s/pdif transmitter block. when clear, the s/pdif transmitter will receive data from the corresponding ac-link output slots. the actual slots are determined by the state of the spas bit. if set, the s/pdif transmitter block will receive data from the adc output. ddm dac direct mode. this bit controls the source to the line and headphone output drivers. when set, the left and right dac directly drive the line and headphone outputs by bypass- ing the audio mixer. when clear, the audio mixer is the source for the line and headphone outputs. amap audio slot mapping. this read/write bit controls whether the cs4201 responds to the codec id to slot mapping as outlined in the ac 97 2.1 specification. this bit is shadowed in the ex- tended audio id register (index 28h) . refer to table 9 for the slot mapping configurations. spas alternate s/pdif slot mapping. this bit controls the mapping of output slots to the s/pdif transmitter. if this bit is 0 (default), the s/pdif transmitter will receive data from the same slots as the dacs. if this bit is 1, alternate (independent) slots will be routed to the s/pdif transmitter. the alternate slots are the same as the sdo2 slots in table 9. sm[1:0] slot map. these bits define the slot mapping for the cs4201 when the amap bit is cleared. refer to table 9 for the slot mapping configurations. default 0080h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 aspm 0 0 ddm amap spas sm1 sm0 0 0 0 0 slot assignment mode codec id slot map amap slot assignments id1 id0 sm1 sm0 dac sdout sdo2 adc spdif for spas = 0 spdif for spas = 1 lrlrlrlr amap mode 000xx 1 34786934 amap mode 101xx 1 34786934 amap mode 210xx 1 7869101178 amap mode 311xx 1 6978101178 slot map mode 0xx00 0 34786934 slot map mode 1xx01 0 7869101178 slot map mode 2xx10 0 6978101178 slot map mode 3xx11 0 511786956 table 9. slot assignments
cs4201 34 ds483pp2 4.25 misc. crystal control register (index 60h) dpc dac phase control. this bit controls the phase of the pcm stream sent to the dac (after src). when cleared the phase of the signal will remain unchanged. when this bit is set, each pcm sample will be inverted before being sent to the dac. 10db this bit, when set, enables an additional boost of 10 db on the selected microphone input. in combination with the 20db boost bit in the microphone volume register (index 0eh) this bit allows for variable boost from 0 db to +30 db in steps of 10 db. crst force cold reset. this bit is used as an override to the new warm reset behavior defined during pr4 powerdown. if this bit is set, an active reset# signal will force a cold reset to the cs4201 during a pr4 powerdown. gpoc general purpose output control. this bit specifies the mechanism by which the status of a general purpose output pin can be controlled. if this bit is cleared, the gpo status is con- trolled through the standard ac 97 method of setting the appropriate bits in output slot 12. if this bit is set, the gpo status is controlled through the gpio pin status register (index 54h) . default 0002h d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 dpc 0 0 reserved 10db crst reserved gpoc reserved 0
cs4201 ds483pp2 35 4.26 s/pdif control register (index 68h) spen s/pdif enable. this bit enables s/pdif data transmission on the spdo/sdo2 pin. the spen bit routes the left and right channel data from the ac 97 controller or from the adc output to the s/pdif transmitter block. the actual data routed to the s/pdif block is con- trolled through the aspm/amap/sm1:0/spas configuration in the ac mode control register (index 5eh) . this bit can only be set if the s2en bit in the serial port control register (index 6ah) ) is 0. when set, spen is a read-only bit and always returns 0. val validity bit. this bit is mapped to the v bit (bit 28) of every sub-frame . if this bit is 0, the signal is suitable for conversion or processing. fs sample rate. this bit indicates the sampling rate for the s/pdif data. the inverse of this bit is mapped to bit 25 of the channel status block. when the fs bit is clear, the sampling fre- quency is 48 khz. when set, the sampling frequency is 44.1 khz. the actual rate at which s/pdif data are being transmitted solely depends on the master clock frequency of the cs4201. the fs bit is merely an indicator to the s/pdif receiver. l generation status. this bit is mapped to bit 15 of the channel status block. for category codes 001xxxx, 0111xxx and 100xxxx a value of 0 indicates original material and a value of 1 indicates a copy of original material. for all other category codes the definition of the l bit is reversed. cc[6:0] category code. these bits are mapped to bits 8-14 of the channel status block. emph data emphasis. this bit is mapped to bit 3 of the channel status block. if the emph bit is 1, 50/15us filter pre-emphasis is indicated. if the bit is 0, no pre-emphasis is indicated. copy copyright. this bit is mapped to bit 3 of the channel status block. if the copy bit is 1 copyright is not asserted and copying is permitted. /audio audio / non-audio. this bit is mapped to bit 1 of the channel status block. if the /audio bit is 0, the data transmitted over s/pdif is assumed to be digital audio. if the /audio bit is 1, non-audio data is assumed. pro pro. this bit is mapped to bit 0 of the channel status block. if the pro bit is 0, consumer use of the audio control block is indicated. if the bit is 1, professional use is indicated. default 0000h. note: for a further discussion of the proper use of the channel status bits see application note an22: overview of digital audio interface data structures [3 ] . d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 spen val 0 fs l cc6 cc5 cc4 cc3 cc2 cc1 cc0 emph copy /audio pro
cs4201 36 ds483pp2 4.27 serial port control register (index 6ah) sden serial data output enable. when set, enables transmission of serial data on the sdout pin. it is also the master enable for s2en and sdsc. the serial data mode and the gpio mode of operation are mutually exclusive. the pra bit in the extended modem id register (index 3ch) must be set prior to setting sden. if pra is 0, sden is cleared and will always re- turns 0. s2en serial port 2 enable. enables transmission of serial data on the spdo/sdo2 pin. serial port 2 and s/pdif modes of operation are mutually exclusive. spen of the s/pdif control register (index 68h) must be 0 and sden must be 1 prior to setting s2en. if spen is 1 or sden is 0, s2en is cleared and will always return 0. sdsc serial clock enable. this bit enables transmission of a serial data clock on the eapd/sclk pin. this bit is mutually exclusive with the eapd bit of the powerdown control/status register (index 26h) . eapd must be 0 and sden must be 1 before sdsc may be set. if eapd is 1 or sden is 0, sdsc will be cleared and always return 0. sdf[1:0] serial data format. these bits determine the serial data format for both serial ports. table 10 lists the available formats. default 0000h the slot assignments for the serial ports sdout and sdo2 are defined by amap and sm1:0 bit of the ac mode control register (index 5eh) . the slot assignments are found in table 9 . 4.28 vendor id1 register (index 7ch) f[7:0] first character of vendor id. 43h - ascii c character. s[7:0] second character of vendor id. 52h - ascii r character. default 4352h, read-only data. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sden00000000000s2ensdscsdf1sdf0 sdf1 sdf0 serial data format 00 i 2 s 0 1 left justified 1 0 right justified, 20-bit data 1 1 right justified, 16-bit data table 10. serial data format selection d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0
cs4201 ds483pp2 37 4.29 vendor id2 register (index 7eh) t[7:0] third character of vendor id. 59h - ascii y character. did[2:0] device id. 100 - cs4201. rev[2:0] revision. 001 - revision a. default 594xh, read-only data. the two vendor id registers provide a means to determine the manufacturer of the ac 97 audio codec. the first three bytes of the vendor id registers contain the ascii code for the first three letters of crystal (cry). the final byte of the vendor id registers is divided into a device id field and a revision field. table 11 lists the currently de- fined device ids. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t7 t6 t5 t4 t3 t2 t1 t0 0 did2 did1 did0 1 rev2 rev1 rev0 did2-did0 part name 000 cs4297 001 cs4297a 010 cs4294/cs4298 011 cs4299 100 cs4201 table 11. device id with corresponding part number
cs4201 38 ds483pp2 5. power management the powerdown control/status register (index 26h) controls the power management functions. bits 14:8 in this register control the internal power- down states of the cs4201. powerdown control is available for individual subsections of the cs4201 by asserting any prx bit alone or in any combina- tion with other prx bits. most powerdown states can be resumed by clearing the corresponding prx bit. pr4 and pr5 require special resume sequenc- es. the pr4 flow is very complex and has different behavior depending on whether the cs4201 is con- figured as a primary or secondary codec. contact cirrus logic for complete detailed functionality. table 12 shows the mapping of the power control bits to the functions they manage. when pr0 is set, the main adcs and the input mux are shut down and the adc bit (bit 0 in the powerdown control/status register (index 26h) ) is cleared indicating the adcs are no longer in a ready state. the same is true for the dacs, the an- alog mixers, and the reference voltage (vrefout). when the pr2 or pr3 bit of the mixer is cleared, the mixer section will begin a power-on process and the corresponding powerdown status bit will be set when the hardware is ready. the pr5 bit disables all internal clocks and powers down the dacs and the adcs, but maintains oper- ation of the bit_clk and the analog mixer. a cold reset is the only way to restore operation to the cs4201 after a global powerdown. to achieve a complete digital powerdown, pr4 and pr5 must be asserted within a single ac output frame. this will also drive bit_clk low. the cs4201 does not automatically mute any input or output when the powerdown bits are set. the software driver controlling the ac 97 device must manage muting the input and output analog signals before putting the part into any power management state. the definition of each prx bit may affect a single subsection or a combination of subsection within the cs4201. table 13 contains the matrix of subsections affected by the respective pr function. table 14 shows the different operating power con- sumptions levels for different powerdown func- tions. pr bit function pr0 main adcs and input mux powerdown pr1 main dacs powerdown pr2 analog mixer powerdown (vref on) pr3 analog mixer powerdown (vref off) pr4 ac-link powerdown (bit_clk off)* pr5 internal clock disable pr6 headphone out powerdown * applies only to primary codec table 12. powerdown pr bit functions
cs4201 ds483pp2 39 pr bit adc dac mixer headphone analog reference ac link internal clock off pr0 pr1 pr2 pr3 pr4 pr5 pr6 table 13. powerdown pr function matrix power state i dvdd (ma) [dvdd=3.3 v] i dvdd (ma) [dvdd=5 v] i avdd1 (ma) i avdd2 (ma) full power + srcs 27.1 44.3 34.9 5.6 full power + s/pdif a a assuming standard resistive load for transformer coupled coaxial s/pdif output (rload = 292 ohm, dvdd = 3.3 v) (rload = 415 ohm, dvdd = 5 v). general: i dvdd s/pdif = i dvdd + dvdd/rload/2 31.9 48.7 34.9 5.6 full power + hp b b hp_out_l, hp_out_r driving 4 vpp into 32 ohm resistive load. 26.3 42.7 34.9 40.6 full power 26.3 42.7 34.9 5.6 adcs off (pr0) 23.4 38.1 26.0 5.6 dacs off (pr1) 24.5 39.3 28.3 5.6 audio off (pr2) 21.5 34.1 2.9 0.8 m a vref off (pr3) 21.2 34.1 2.8 0.8 m a hp amp off (pr6) 26.3 42.7 33.1 27 m a ac-link off (pr4) 20.9 35.2 34.9 5.6 internal clocks off (pr5) 3.8 6.4 19.8 5.6 digital off (pr4+pr5) 14 m a28 m a 19.8 5.6 pr3+pr4+pr5 14 m a28 m a 2.3 0.5 m a reset 1.5 m a8 m a 2.9 0.8 m a table 14. power consumption by powerdown mode
cs4201 40 ds483pp2 6. analog hardware description the analog input hardware consists of four line-level stereo inputs (line_l/r, cd_l/gnd/r, video_l/r, and aux_l/r), two selectable mono microphone inputs (mic1 and mic2), and two mono inputs (pc_beep and phone). the analog output hardware consists of a mono output (mono_out), a stereo line output (line_out_l/r), and a stereo headphone output (hp_out_l/r). this section describes the analog hardware needed to interface with these pins. the designs presented in this section comply with spec- ifications detailed in chapter 17 of the microsoft ? document, pc design guidelines [7], referred to as pc 99. for information on emi reduction tech- niques refer to the application note an165: cs4297a/cs4299 emi reduction techniques [5]. 6.1 analog inputs all analog inputs to the cs4201, including cd_gnd, should be capacitively coupled to the input pins. unused analog inputs should be con- nected together and then connected through a ca- pacitor to analog ground or tied to the vrefout line directly. the maximum allowed voltage for analog inputs, except the microphone input, is 1 v rms . for the microphone input the maximum allowed volt- age depends on the selected boost setting. 6.1.1 line-level inputs figure 10 shows circuitry for a line-level input. this design can be replicated for the line, video and aux inputs. this design attenuates the input by 6 db, bringing the signal from the pc 99 specified 2v rms , to the cs4201 maximum allowed 1 v rms . 6.1.2 cd input the cd line-level input has an extra pin, cd_gnd, providing a pseudo-differential input for both cd_l and cd_r. this pin takes the common-mode noise out of the cd inputs when connected to the cd analog source ground. follow- ing the provided reference designs in figure 11 and figure 12 provides extra attenuation of common mode noise coming from the cd-rom drive, thereby producing a higher quality signal. one per- cent resistors are recommended since closely matched resistor values provide better com- mon-mode attenuation of unwanted signals. the circuit shown in figure 11 can be used to attenuate a 2 v rms cd input signal by 6 db. the circuit shown in figure 12 can be used for a 1 v rms cd in- put signal. line_in_r line_in_l 6.8 k w 1.0 m f 1.0 m f agnd agnd 6.8 k w 6.8 k w 6.8 k w figure 10. line input (replicate for video and aux) figure 11. differential 2 v rms cd input (all resistors 1%) 6.8 k w cd_l cd_com cd_r 1.0 m f cd_l cd_r cd_gnd 6.8 k w 1.0 m f 3.4 k w 6.8 k w 2.2 m f 3.4 k w 6.8 k w agnd figure 12. differential 1 v rms cd input 100 w cd_l cd_com cd_r 1.0 m f cd_l cd_r cd_gnd 100 w 1.0 m f 100 w 47 k w 2.2 m f 47 k w 47 k w agnd
cs4201 ds483pp2 41 6.1.3 microphone inputs figure 13 illustrates a microphone input circuit that supports lower gain dynamic and phantom-pow- ered microphones that use the right channel (ring) of the jack for power. it also supports the recom- mended advanced frequency response for voice recognition as specified in pc 99. note the micro- phone input to the cs4201 has an integrated pre-amplifier. using combinations of the 10db bit in the misc. crystal control register (index 60h) and the 20db bit in the microphone volume regis- ter (index 0eh) ), the pre-amplifier gain can be set to 0 db, 10 db, 20 db, or 30 db. 6.1.4 pc beep input the pc_beep input is useful for mixing the output of the beeper (timer chip), provided in many pcs, with the other audio signals. when the cs4201 is held in reset, pc_beep is passed directly to the line output. this allows the system sounds or beeps to be available before the ac 97 interface has been activated. this feature is affected by the hpcfg pin; see section 12 for the pin description. figure 14 illustrates a typical input circuit for the pc_beep input. if pc_beep is driven from a cmos gate, the 4.7 k w resistor should be tied to analog ground instead of +5 va. although this in- put is described for a low-quality beeper, it is of the same high-quality as all other analog inputs and may be used for other purposes. 6.1.5 phone input one application of the phone input is to interface to the output of a modem analog front end (afe) device so that modem dialing signals and protocol negotiations may be monitored through the audio system. figure 15 shows a design for a modem connection where the output is fed from the cs4201 mono_out pin through a divider. the divider ratio shown does not attenuate the signal, providing an output voltage of 1 v rms . if a lower output voltage is desired, the resistors can be re- placed with appropriate values, as long as the total load on the output is kept greater than 10 k w . the phone input is attenuated by 6 db to accommo- date a line-level source of 2 v rms . 0.1 m f x7r 100 w 0.1 m f x7r mic1/mic2 10 m f elec agnd +5va 2.2 k w 1.5 k w agnd agnd figure 13. microphone input 4.7 k w pc_beep +5va (low noise) or agnd if cmos source pc-beep-bus 47 k w 2.7 nf x7r 0.1 m f x7r agnd figure 14. pc_beep input phone mono_out phone mono_out 6.8 kw 1.0 m f 0 w 6.8 k w 1.0 m f 47 k w agnd figure 15. modem connection
cs4201 42 ds483pp2 6.2 analog outputs each analog output is dc-biased up to the vrefout voltage signal reference which is nominally 2.4 v. this requires the outputs be ac-coupled to exter- nal circuitry (ac loads must be greater than 10 k w for line_out or 32 w for hp_out). the hp_out coupling capacitors should be 220 m f or greater in order to prevent low frequency roll-off. in addition, the line_out_l, line_out_r, and mono_out pins require 680 pf to 1000 pf npo dielectric capacitors between the correspond- ing pin and analog ground. 6.2.1 stereo outputs the line_out and hp_out stereo outputs de- pend on the configuration of the hpcfg pin. as shown in figure 16, if the hpcfg pin is left float- ing, the part behaves as specified in ac 97. as shown in figure 17, if the hpcfg pin is grounded, the part behaves as if hp_out was the only out- put. in this case, line_out will be muted, the master volume register (index 02h) will control hp_out and pc_beep will be routed to hp_out during reset. 6.2.2 mono output the mono output, mono_out, can be either a sum of the left and right output channels, attenuat- ed by 6 db to prevent clipping at full scale, or the selected mic signal. the mono out channel can drive the pc internal mono speaker using an appro- priate buffer circuit. 6.3 miscellaneous analog signals the aflt1 and aflt2 pins must have a 1000 pf npo capacitor to analog ground. these capacitors provide a single-pole low-pass filter at the inputs to the adcs. this makes low-pass filters at each ana- log input pin unnecessary. the refflt pin must have a 2.2 m f and 0.1 m f capacitor connected to analog ground with a short, wide trace to this pin (see figure 17 in section 11, grounding and layout , for an example). the 2.2 m f capacitor must not be replaced by any other value and must be ceramic with low leakage cur- rent. electrolytic capacitors should not be used. no other connection should be made, as any coupling onto this pin will degrade the analog performance of the cs4201. likewise, digital signals should be kept away from refflt for similar reasons. hp_out_r hp_out_c hp_out_l 220 m f elec 220 m f elec 1 m f elec 10 k w 10 k w agnd agnd line_out_r line_out_l 10 m f elec 10 m f elec 220 k w 220 k w agnd agnd headphone jack line out jack hpcfg 1000 pf 1000 pf agnd figure 16. line out and headphone out setup hp_out_r hp_out_c hp_out_l 220 m f elec 220 m f elec 1 m f elec 10 k w 10 k w agnd agnd line_out_r line_out_l headphone jack hpcfg agnd figure 17. line out/headphone out setup
cs4201 ds483pp2 43 6.4 power supplies the power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog per- formance. one analog power pin, avdd2, supplies power to the headphone output circuitry on the cs4201. the other analog power pin, avdd1, sup- plies power to the rest of the cs4201 analog cir- cuitry. the +5 v analog supply should be generated from a voltage regulator (7805 type) connected to a +12 v supply. this helps isolate the analog circuit- ry from noise typically found on +5 v digital sup- plies. a typical voltage regulator circuit for analog power using a mc78m05cdt +5v regulator is shown in figure 18. the digital power pins, dvdd1 and dvdd2, should be connected to the same digi- tal supply as the controllers ac-link interface. since the digital interface on the cs4201 may op- erate at either +3.3 v or +5 v, proper connection of these pins will depend on the digital power supply of the controller. 6.5 reference design figure 19 shows a simple reference design for the cs4201 using the internal headphone amplifier in a line out\headphone out setup. figure 18. +5v analog voltage regulator +12vd agnd dgnd +5va 0.1 f y5v 10f elec + 10f elec + mc78m05cdt out 3 gnd 2 in 1 0.1f y5v
cs4201 44 ds483pp2 r17 6.8k c17 220uf elec + r11 10k r5 6.8k c33 22pf npo c7 10uf elec + c12 10uf elec + c1 0.1uf x7r r6 6.8k c32 22pf npo j1 2x1hdr-sn/pb 1 2 r3 6.8k c9 0.1uf x7r c20 10uf elec + c23 1000pf npo j2 4x1hdr-au 1 2 3 4 c25 0.01uf x7r r7 47 c22 0.1uf x7r c15 220uf elec + j7 phono-1/8 4 3 5 2 1 c2 2700pf x7r y1 24.576 mhz r1 47k c30 10uf elec + r16 6.8k r15 6.8k c11 0.1uf x7r r4 6.8k r19 2.2k j4 phono-1/8 4 3 5 2 1 r20 100 c28 0.1uf x7r c29 0.1uf x7r c3 10uf elec + c5 0.1uf x7r u1 mc78m05acdt out 3 gnd 2 in 1 c4 0.1uf x7r c10 0.1uf c6 10uf elec c8 0.1uf x7r r2 4.7k r8 47 c27 1000pf npo r18 8.2k r13 10k c24 1000pf npo c19 10uf elec + j5 phono-1/8 4 3 5 2 1 j3 4x1hdr-au 1 2 3 4 r10 100k c13 10uf elec + r12 100k c16 10uf elec + r9 100k r14 6.8k c14 10uf elec + c26 0.1uf x7r j6 totx-173 1 2 3 4 5 6 c18 1uf elec c21 2.2uf z5u r21 1.5k 60 mil trace gnd_tie u2 cs4201 line_out_r 36 mono_out 37 avdd2 38 hp_out_l 39 gpio1/sdout 44 hp_out_r 41 avss2 42 gpio0/lrclk 43 hp_out_c 40 flto 34 flti 33 flt3d 32 hpcfg 31 dvdd1 1 xtl_in 2 xtl_out 3 dvss1 4 sdata_out 5 bit_clk 6 dvss2 7 sdata_in 8 sync 10 dvdd2 9 reset# 11 pc_beep 12 phone 13 aux_l 14 aux_r 15 video_l 16 video_r 17 cd_l 18 cd_gnd 19 cd_r 20 mic1 21 mic2 22 line_in_l 23 line_in_r 24 avdd1 25 avss1 26 refflt 27 vrefout 28 aflt1 29 aflt2 30 spdo/sdo2 48 eapd/sclk 47 id1# 46 id0# 45 line_out_l 35 agnd agnd agnd agnd dgnd agnd agnd agnd dgnd agnd agnd dgnd +5va +12v agnd agnd dgnd +3.3vd dgnd dgnd +5vd agnd agnd agnd agnd +5va dgnd agnd async arst# abitclk asdout asdin pc speaker in cd in mic in aux in line in line out/ headphone jack s/pdif out ac link pci audio controller or ich controller mic in -3 db roll-off frequencies at 60 hz. and 16 khz in accordance with pc-99 (50 ppm) tie at one point only under the codec + figure 19. cs4201 reference design
cs4201 ds483pp2 45 7. sony/philips digital interface (s/pdif) the s/pdif digital output is used to interface the cs4201 to consumer audio equipment external to the pc. this output provides an interface for stor- ing digital audio data or playing digital audio data to digital speakers. figure 20 illustrates the circuit necessary for implementation of the iec-958 opti- cal or consumer interface. for further information on s/pdif operation, see the application note an22: overview of digital audio interface data structures [3] . also see application note an134: aes and s/pdif recommended transformers [4] for information on s/pdif recommended trans- formers. 1 2 3 4 5 6 0.1 m f r 2 r 1 j-rca-r4-pcb dgnd dvdd r 1 r 2 spdo/sdo2 s/pdif_out totx-173 spdo/sdo2 +5v_pci dgnd 8.2 k w dgnd dgnd 3.3v 247.5 w 107.6 w 5v 375 w 93.75 w figure 20. consumer and optical s/pdif outputs
cs4201 46 ds483pp2 8. clocking the cs4201 may be operated as the primary or sec- ondary codec. as a primary codec, the system clock for the ac-link may be generated from an ex- ternal 24.576 mhz clock source, a 24.576 mhz crystal, or use the internal phase locked loop (pll). the pll allows the cs4201 to accept exter- nal clock frequencies other than 24.576 mhz. the cs4201 uses the presence or absence of a valid clock on the xtl_in pin in conjunction with the id[1:0]# pins to determine the clocking configura- tion. 8.1 pll operation (external clock) the pll mode is activated if a valid clock is present on xtl_in during the rising edge of re- set#. once pll mode is entered, the xtl_out pin is redefined as the pll loop filter, as shown in figure 21. the id[1:0]# inputs determine the con- figuration of the internal divider ratios required to generate the 12.288 mhz bit_clk output, see table 15 for additional details. in pll mode, the cs4201 is configured as a primary codec indepen- dent of the state of the id[1:0]# pins. if 24.576 mhz is chosen as the external clock input (id[1:0]# left open or both pulled to logic 1), the pll is disabled and the clock is used directly. the loop filter is not required and xtl_out is left un- connected. for all other clock input choices, the loop filter is required. the id[1:0] bits of the ex- tended audio id register (index 28h) and the ex- tended modem id register (index 3ch) will always report 0 in pll mode. 8.2 24.576 mhz crystal operation if a valid clock is not present on xtl_in during the rising edge of reset#, the device disables the pll input and latches the state of the id[1:0]# in- puts. if the id[1:0]# inputs are both pulled high or left floating, the device is configured as a primary codec. an external 24.576 mhz crystal is used as the system clock as shown in figure 22. if either id[1:0]# inputs are pulled low, the device is deter- mined to be a secondary codec. the bit_clk pin is configured as an input and the cs4201 is driven from the 12.288 mhz bit_clk of the primary co- dec. the id[1:0] bits of the extended audio id register (index 28h) and the extended modem id register (index 3ch) will report the state of the id[1:0]# inputs. figure 21. pll external loop filter xtl_out xtl_in 2.2 k w 0.022 uf 220 pf clock source xtl_out xtl_in 22 pf 22 pf 24.576 mhz figure 22. external crystal
cs4201 ds483pp2 47 external clock on xtl_in id1# id0# ac-link timing mode codec id clock source clock rate (mhz) pll active application notes yes 1 1 primary 0 external 24.576 no clock generator driving xtl_in yes 1 0 primary 0 external 14.31818 yes external clock source driving xtl_in loop filter connected to xtl_out yes 0 1 primary 0 external 27.000 yes yes 0 0 primary 0 external 48.000 yes no 1 1 primary 0 xtal 24.576 no crystal connected to xtl_in, xtl_out no 1 0 secondary 1 bit_clk 12.288 no bit_clk from primary codec driving bit_clk on all secondary codecs no 0 1 secondary 2 bit_clk 12.288 no no 0 0 secondary 3 bit_clk 12.288 no table 15. clocking configurations
cs4201 48 ds483pp2 9. serial data ports 9.1 overview the cs4201 features two serial data ports that can be used to send ac-link data to one or two external stereo dacs to support a total of up to six audio channels. the first serial port takes the digital au- dio data from the sdout slots and the second se- rial port takes the digital audio data from the sdo2 slots. see table 9 for the actual slots used depend- ing on configuration. each serial port consists of four signals: mclk, sclk, lrclk, and sdata. the existing 256 fs bit_clk will be used as mclk. all clocks are shared between the two serial ports with only the sdata pins being separate; sdout for the first serial port and sdo2 for the second serial port. figure 23 shows the principal connections for multi-channel applications of the cs4201. the serial data port is controlled by the sden, s2en, and sdsc bits in the serial port control register (index 6ah) . all the pins for the serial data ports are multiplexed with other functions and can- not be used unless the other function is disabled or powered down. refer to section 10, exclusive functions , for additional information on control- ling the serial data ports. some audio dacs can run in an internal sclk mode where sclk is internal- ly derived from mclk and lrclk. in this case, sclk generation in the cs4201 is optional. a feature has been designed into the cs4201 that allows the phase of the internal dac to be re- versed. this is necessary since it is unknown what phase response a particular external dac might have. also, the phase response of the internal dac can vary depending on the path determined by the pop bit in the general purpose register (index 20h) , the ddm bit in the ac mode control regis- ter (index 5eh) and which output (line_out or hp_out) is being used. this feature assures that all dacs in a system have the same phase response to maintain the accuracy of spatial cues. the dac phase is controlled by the dpc bit in the misc. crystal control register (index 60h) . please note the data sent to the serial ports is straight from the ac-link. there is no src and no volume control available on this data, so it is the re- sponsibility of the controller or host software to provide this functionality if desired. 9.2 serial data formats in order to support a wide variety of serial audio dacs, the cs4201 can provide serial data in four different formats. the desired format is selected through the sdf[1:0] bits in the serial port con- trol register (index 6ah) . both serial ports, if en- abled, use the same serial data format. in all cases, lrclk will be synchronous with fs, and sclk will be 64 fs (bit_clk / 4). serial data is transi- tioned by the cs4201 on the falling edge of sclk and latched by the dac on the next rising edge. se- rial data is shifted out msb first in all supported formats, but lrclk polarity as well as data justi- fication, alignment, and resolution vary. table 16 shows the principal characteristics of each format. sdf[1:0] lrclk polarity data justification data alignment (msb vs. lrclk) data resolution timing diagram recommended dac 0 0 negative left justified 1 sclk delayed 20-bit figure 24 cs4334 0 1 positive left justified not delayed 20-bit figure 25 cs4335 1 0 positive right justified not delayed 20-bit figure 26 cs4337 1 1 positive right justified not delayed 16-bit figure 27 cs4338 table 16. serial data formats and compatible dacs
cs4201 ds483pp2 49 8 5 4 3 2 1 4 3 2 18 5 aoutl aoutr sdata dem#/sclk lrck mclk gpio1/sdout spdo/sdo2 44 48 47 43 eapd/sclk gpio0/lrclk line_out_l line_out_r bit_clk 6 36 35 cs4201 cs4334 aoutl aoutr sdata dem#/sclk lrck mclk cs4334 270k 270k 10uf elec 10uf elec 47k 47k 560 560 2700pf 2700pf left surround right surround 270k 270k 10uf elec 10uf elec 47k 47k 560 560 2700pf 2700pf center lfe agnd agnd agnd agnd left front right front agnd agnd 10uf elec 10uf elec 1000pf agnd 1000pf 220k 220k agnd figure 23. serial data port connection diagram
cs4201 50 ds483pp2 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 m s b-1-2-3-4-5 +3 +2 +1 lsb +5 +4 m s b-1-2-3-4 figure 24. serial data format 0 (i 2 s) lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 m sb-1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 m sb-1 -2 -3 -4 figure 25. serial data format 1 (left justified) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 19 18 19 18 figure 26. serial data format 2 (right justified, 20-bit data) lrck sclk left channel right channel sdata 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 figure 27. serial data format 3 (right justified, 16-bit data)
cs4201 ds483pp2 51 10. exclusive functions some of the digital pins on the cs4201 have mul- tiplexed functionality. these functions are mutual- ly exclusive and cannot be requested at the same time. the following pairs of functions are mutually exclusive: ? gpio and serial data port (gpio0 pin is shared with lrclk pin and gpio1 pin is shared with sdout pin) ? eapd and serial data port serial clock (eapd pin is shared with sclk pin) ? s/pdif and second serial data port (spdo pin is shared with sdo2 pin) there is no priority assigned to these operational modes. a function currently in use must be dis- abled or powered down before the corresponding exclusive function can be enabled. the following control bits for these functions will behave differ- ently than normal bits: the eapd bit in the power- down control/status register (index 26h) , the pra bit in the extended modem status/control register (index 3eh) , the spen bit in the s/pdif control register (index 68h) , and the sden, s2en and sdsc bits in the serial port control register (in- dex 6ah) . these bits can become read-only if they control a feature that is currently unavailable be- cause the corresponding exclusive feature is al- ready in use. 11. grounding and layout figure 28 shows the conceptual layout for the cs4201. the decoupling capacitors should be lo- cated physically as close to the pins as possible. al- so, note the connection of the refflt decoupling capacitors to the ground return trace connected di- rectly to the ground return pin, avss1. it is strongly recommended that separate analog and digital ground planes be used. separate ground planes keep digital noise and return currents from modulating the cs4201 ground potential and de- grading performance. the digital ground pins should be connected to the digital ground plane and kept separate from the analog ground connections of the cs4201 and any other external analog cir- cuitry. all analog components and traces should be located over the analog ground plane and all digital components and traces should be located over the digital ground plane. the common connection point between the two ground planes (required to maintain a common ground voltage potential) should be located under the cs4201. the ac-link digital interface connec- tion traces should be routed such that the digital ground plane lies underneath these signals (on the internal ground layer). this applies along the entire length of these traces from the ac 97 controller to the cs4201. refer to the application note an18: layout and design rules for data converters and other mixed signal devices [2] for more information on layout and design rules.
cs4201 52 ds483pp2 . analog ground to digital ground pin 1 0.1 f 1000 pf npo 2.2f to analog ground to +5va to +5vd 0.1 f y5v to +5vd 0.1 f y5v y5v 0.1 f y5v to +5va avdd2 avss2 aflt2 aflt1 refflt avss1 avdd1 dvss1 dvss2 dvdd2 dvdd1 vrefout to via to analog ground figure 28. conceptual layout for the cs4201
cs4201 ds483pp2 53 12. pin descriptions 6 2 4 8 10 1 3 5 7 9 11 12 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mono_out avdd2 hp_out_l hp_out_c hp_out_r avss2 gpio0/lrclk gpio1/sdout id0# id1# eapd/sclk spdo/sdo2 dvdd1 xtl_in xtl_out dvss1 sdata_out bit_clk dvss2 sdata_in dvdd2 sync reset# pc_beep phone aux_l aux_r video_l video_r cd_l c d _g n d cd_r mic1 mic2 line_in_l line_in_r line_out_r line_out_l flto flti flt3d hpcfg aflt2 aflt1 vrefout refflt avss1 avdd1 cs4201 tqfp
cs4201 54 ds483pp2 audio i/o pc_beep - analog mono source, input, pin 12 the pc_beep input is intended to allow the pc system post (power on self-test) tones to pass through to the audio subsystem. the pc_beep input has two connections: the first connection is to the analog output mixer, the second connection is directly to the line_out stereo outputs (if hpcfg is floating) or through the headphone amplifier to the hp_out pins (if hpcfg is tied low). while the reset# pin is actively being asserted to the cs4201, the pc_beep bypass path to the line_out/hp_out outputs is enabled. while the cs4201 is in the normal operation mode with reset# de-asserted, pc_beep is a monophonic source to the analog output mixer. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. phone - analog mono source, input, pin 13 this analog input is a monophonic source to the analog output mixer. it is intended to be used as a modem subsystem input to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic1 - analog mono source, input, pin 21 this analog input is a monophonic source to the analog output mixer. it is intended to be used as a desktop microphone connection to the audio subsystem. the cs4201 internal mixer microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. mic2 - analog mono source, input, pin 22 this analog input is a monophonic source to the analog output mixer. it is intended to be used as an alternate microphone connection to the audio subsystem. the cs4201 internal mixer microphone input is mux selectable with either mic1 or mic2 as the input. the maximum allowable input is 1 v rms (sinusoidal). this input is internally biased at the vrefout voltage reference and requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. line_in_l, line_in_r - analog line source, inputs, pins 23 and 24 these inputs form a stereo input pair to the cs4201. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. cd_l, cd_r - analog cd source, inputs, pins 18 and 20 these inputs form a stereo input pair to the cs4201. it is intended to be used for the red book cd audio connection to the audio subsystem. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground.
cs4201 ds483pp2 55 cd_gnd - analog cd common source, input, pin 19 this analog input is used to remove common mode noise from red book cd audio signals. the impedance on the input signal path should be one half the impedance on the cd_l and cd_r input paths. this pin requires ac-coupling to external circuitry. if this input is not used, it should be connected to the vrefout pin or ac-coupled to analog ground. video_l, video_r - analog video audio source, inputs, pins 16 and 17 these inputs form a stereo input pair to the cs4201. it is intended to be used for the audio signal output of a video device. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. aux_l, aux_r - analog auxiliary source, inputs, pins 14 and 15 these inputs form a stereo input pair to the cs4201. the maximum allowable input is 1 v rms (sinusoidal). these inputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. if these inputs are not used, they should both be connected to the vrefout pin or both ac-coupled, with separate ac-coupling caps, to analog ground. line_out_l, line_out_r - analog line level, outputs, pins 35 and 36 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 1 v rms (sinusoidal). these outputs are internally biased at the vrefout voltage reference and require either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage. these pins need a 680-1000 pf npo capacitor attached to analog ground. hp_out_l, hp_out_r - analog headphone, outputs, pins 39 and 41 these signals are analog outputs from the stereo output mixer. the full-scale output voltage for each output is nominally 4 v pp . these outputs are internally biased at the vrefout voltage reference and require ac-coupling to external circuitry. the hp_out pins can directly drive resistive loads as low as 32 w (such as standard consumer headphones). capacitive loading must not exceed 200 pf/pin. the outputs are short circuit protected for infinite duration. hp_out_c - analog headphone output common source, input, pin 40 this analog input is used to remove common mode noise from the headphone outputs. this is achieved by biasing the headphone amplifier with the common mode noise on the headphone amplifier ground plane. this pin should be ac-coupled through a 1 m f elec capacitor to analog ground (avss2) near the headphone jack. mono_out - analog mono line level, output, pin 37 this signal is an analog output from the stereo-to-mono mixer. the full-scale output voltage for this output is nominally 1 v rms (sinusoidal). this output is internally biased at the vrefout voltage reference and requires either ac-coupling to external circuitry or dc-coupling to a buffer op-amp biased at the vrefout voltage. this pin needs a 680 - 1000 pf npo capacitor attached to analog ground.
cs4201 56 ds483pp2 analog reference, filters, and configuration refflt - internal reference voltage, input, pin 27 this is the voltage reference used internal to the part. a 0.1 m f and a 2.2 m f capacitor with short, wide traces must be connected to this pin. no other connections should be made to this pin. do not use an electrolytic 2.2 m f capacitor; use type z5u or y5v. two 1.0 m f capacitors in parallel can be used in place of the 2.2 m f capacitor. vrefout - voltage reference, output, pin 28 all analog inputs and outputs are centered around vrefout which is nominally 2.4 volts. this pin may be used to level shift external circuitry. it can also drive up to 5 ma of dc which can be used for microphone bias. aflt1 - left channel antialiasing filter, input, pin 29 this pin needs a 1000 pf npo capacitor attached to analog ground. aflt2 - right channel antialiasing filter, input, pin 30 this pin needs a 1000 pf npo capacitor attached to analog ground. flti, flto - filter input/filter output, pins 33 and 34 a 1000 pf capacitor must be attached between flti and flto if the 3d function is used. flt3d - 3d filter, pin 32 a 0.01 m f x7r capacitor must be attached from this pin to agnd if the 3d function is used. hpcfg - headphone configuration, input, pin 31 this pin is the configuration control for the signal routing to the headphone amplifier. if this pin is left floating, line_out and hp_out function as defined in the ac 97 specification. if this pin is grounded, the hp_out behaves as a buffered line output. the line_out outputs are muted, the control for the hp_out will be master volume register (index 02h) and pc_beep is routed to hp_out during reset. the pin is internally pulled up to the analog supply voltage. ac-link reset# - ac 97 chip reset, input, pin 11 this active low signal is the asynchronous cold reset input to the cs4201. the cs4201 must be reset before it can enter normal operating mode. sync - ac-link serial port sync pulse, input, pin 10 this signal is the serial port timing signal for the ac-link. its period is the reciprocal of the maximum sample rate, 48 khz, and is generated by the ac 97 controller synchronous to bit_clk. sync is also an asynchronous input when the cs4201 is configured as a primary device and is in a pr4 powerdown state. a series terminating resistor of 47 w should be connected on this signal close to the controller.
cs4201 ds483pp2 57 bit_clk - ac-link serial port master clock, input/output, pin 6 this input/output signal controls the master clock timing for the ac-link. when the cs4201 is in primary mode, this signal is a 12.288 mhz output clock signal derived from either a 24.576 mhz crystal or from the internal pll based on the xtl_in input clock. when the cs4201 is in secondary mode, this signal is an input which controls the ac-link serial interface and generates all internal clocking including the ac-link serial interface timing and the analog sampling clocks. a series terminating resistor of 47 w should be connected on this signal close to the cs4201 in primary mode or close to the bit_clk source in secondary mode. sdata_out - ac-link serial data input stream to ac 97, input, pin 5 this input signal receives the control information and digital audio output streams. the data is clocked into the cs4201 on the falling edge of bit_clk. a series terminating resistor of 47 w should be connected on this signal close to the controller. sdata_in - ac-link serial data output stream from ac 97, output, pin 8 this output signal transmits the status information and digital audio input streams from the adcs. the data is clocked out of the cs4201 on the rising edge of bit_clk. a series terminating resistor of 47 w should be connected on this signal as close to the cs4201 as possible. clock and configuration xtl_in - crystal input/clock input, pin 2 this pin requires either a 24.576 mhz crystal, with the other pin attached to xtl_out, or an external cmos clock. the crystal must be designed for fundamental mode, parallel resonance operation. when configured as a secondary codec, all timing is derived from the bit_clk input signal; this pin should be left floating. see section 8, clocking , for additional details. xtl_out - crystal output/ pll loop filter, pin 3 used for a crystal placed between this pin and xlt_in. if an external clock is used on xtl_in, this pin is configured as the loop filter for the internal pll circuitry. see section 8, clocking , for additional details. id1#, id0# - codec id, inputs, pins 45 and 46 these pins select the codec id for the cs4201, as well as determine the rate of the incoming clock in pll mode. they are only sampled after the rising edge of reset#. these pins are internally pulled up to the digital supply voltage and should be left floating for logic 0 or tied to digital ground for logic 1. misc. digital interfaces spdo/sdo2 - sony/philips digital interface output / serial data output 2, pin 48 this pin generates the s/pdif digital output from the cs4201 when the spen bit in the s/pdif control register (index 68h) is set. this output may be used to directly drive a resistive divider and coupling transformer to an rca-type connector for use with consumer audio equipment. this pin also provides the serial data for the second serial data port when the s2en bit in the serial port control register (index 6ah) is set. these two functions are mutually exclusive. when neither function is being used this output is driven to a logic 0.
cs4201 58 ds483pp2 eapd/sclk - external amplifier power down / serial clock, output, pin 47 this signal is designated as a power down control for audio amplifiers external to the cs4201. the output is determined by the eapd bit in the powerdown control/status register (index 26h) and is low by default. when the serial data interface is enabled, this output is configured as the serial clock for both serial data ports when the sdsc bit in the serial port control register (index 6ah) is set. gpio0/lrclk - general purpose i/o / left-right clock, input/output, pin 43 this pin is a general purpose i/o pin that can be used to interface with various external circuitry. when configured as an input, it functions as a schmitt triggered input with 350 mv hysteresis at 5 v and 220 mv hysteresis at 3.3 v. when configured as an output, it can function as a normal cmos output (4 ma drive) or as an open drain output. this pin also provides the l/r clock for both serial data ports when the sden bit in the serial port control register (index 6ah) is set. this bit powers up in the high impedance state for backward compatibility. gpio1/sdo1 - general purpose i/o / serial data ouput 1, input/output, pin 44 this pin is a general purpose i/o pin that can be used to interface with various external circuitry. when configured as an input, it functions as a schmitt triggered input with 350 mv hysteresis at 5 v and 220 mv hysteresis at 3.3 v. when configured as an output, it can function as a normal cmos output (4 ma drive) or as an open drain output. this pin also provides the serial data for the first serial data port when the sden bit in the serial port control register (index 6ah) is set. this bit powers up in the high impedance state for backward compatibility. power supplies dvdd1, dvdd2 - digital supply voltage, pins 1 and 9 digital supply voltage for the ac-link section of the cs4201. these pins can be tied to +5 v digital or to +3.3 v digital. the cs4201 and controllers ac-link should share a common digital supply. dvss1, dvss2 - digital ground, pins 4 and 7 digital ground connection for the ac-link section of the cs4201. these pins should be isolated from analog ground currents. avdd1, avdd2 - analog supply voltage, pins 25 and 38 analog supply voltage for the analog and mixed signal section of the cs4201 (avdd1) as well as the headphone amplifier (avdd2). these pins must be tied to the analog +5 v power supply. it is strongly recommended that +5 v be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. avss1, avss2 - analog ground, pins 26 and 42 ground connection for the analog, mixed signal, and substrate sections of the cs4201 (avss1) as well as the headphone amplifier (avss2). these pins should be isolated from digital ground currents.
cs4201 ds483pp2 59 13. parameter and term definitions ac 97 specification refers to the audio codec 97 component specification ver 2.1 published by intel ? corporation [6]. ac 97 controller or controller refers to the control chip which interfaces to the audio codec ac-link. this has been also called dc 97 for digital controller 97 [6]. ac 97 registers or codec registers refers to the 64-field register map defined in the ac 97 specification. adc refers to a single analog-to-digital converter in the cs4201. adcs refers to the stereo pair of analog-to-digital converters. the cs4201 adcs have 18-bit resolution. dac a single digital-to-analog converter in the cs4201 dacs refers to the stereo pair of digital-to-analog converters. the cs4201 dacs have 20-bit resolution. src sample rate converter. converts data derived at one sample rate to a differing sample rate. the cs4201 operates at a fixed sample frequency of 48 khz. the internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 khz. codec refers to the chip containing the adcs, dacs, and analog mixer. in this data sheet, the codec is the cs4201. fft fast fourier transform. resolution the number of bits in the output words to the dacs, and in the input words to the adcs. differential nonlinearity the worst case deviation from the ideal code width. units in lsb. db fs a db fs is defined as db relative to full-scale. the a indicates an a weighting filter was used. frequency response (fr) fr is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. dynamic range (dr) dr is the ratio of the rms full-scale signal level divided by the rms sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a.
cs4201 60 ds483pp2 total harmonic distortion plus noise (thd+n) thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. it is tested using a -3 db fs input signal and is measured over a 20 hz to 20 khz bandwidth with units in db fs. signal to noise ratio (snr) snr, similar to dr, is the ratio of an arbitrary sinusoidal input signal to the rms sum of the noise floor, in the presence of a signal. it is measured over a 20 hz to 20 khz bandwidth with units in db. s/pdif sony/phillips digital interface. this interface was established as a means of digitally interconnecting consumer audio equipment. the documentation for s/pdif has been superseded by the iec-958 consumer digital interface document. interchannel isolation the amount of 1 khz signal present on the output of the grounded ac-coupled line input channel with 1 khz, 0 db, signal present on the other line input channel. units are in db. interchannel gain mismatch for the adcs, the difference in input voltage to get an equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units are in db. paths a-d: analog in, through the adc, onto the serial link. d-a: serial interface inputs through the dac to the analog output. a-a: analog in to analog out (analog mixer). pll phase lock loop. circuitry for generating a desired clock from an external clock source.
cs4201 ds483pp2 61 14. references 1) cirrus logic, audio quality measurement specification , version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) cirrus logic, an18: layout and design rules for data converters and other mixed signal devices , version 6.0, february 1998. 3) cirrus logic, an22: overview of digital audio interface data structures , version 2.0, february 1998. 4) cirrus logic, an134: aes and s/pdif recommended transformers , version 2, april 1999. 5) cirrus logic, an165: cs4297a/cs4299 emi reduction techniques , version 1.0, september 1999. 6) intel ? , audio codec 97 component specification , revision 2.1, may 1998. http://developer.intel.com/ial/scalableplatforms/audio/index.htm 7) microsoft ? , pc 99 system design guide , version 1.0, july 1999. http://www.microsoft.com/hwdev/desguid/ 8) intel ? 82801aa (ich) and 82801ab (ich0) i/o controller hub , june 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm
cs4201 62 ds483pp2 15. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e l b a1 a
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